1357 lines
47 KiB
Plaintext
1357 lines
47 KiB
Plaintext
config ESP_HOSTED_ENABLED
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bool
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default y if ESP_WIFI_REMOTE_ENABLED && ESP_WIFI_REMOTE_LIBRARY_HOSTED
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default n
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menu "ESP-Hosted config"
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depends on ESP_HOSTED_ENABLED
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# Co-processor selection done in Wi-Fi Remote Component
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comment "ESP32 is Slave Target from Wi-Fi Remote Component"
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depends on SLAVE_IDF_TARGET_ESP32
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comment "ESP32-S2 is Slave Target from Wi-Fi Remote Component"
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depends on SLAVE_IDF_TARGET_ESP32S2
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comment "ESP32-S3 is Slave Target from Wi-Fi Remote Component"
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depends on SLAVE_IDF_TARGET_ESP32S3
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comment "ESP32-C2 is Slave Target from Wi-Fi Remote Component"
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depends on SLAVE_IDF_TARGET_ESP32C2
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comment "ESP32-C3 is Slave Target from Wi-Fi Remote Component"
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depends on SLAVE_IDF_TARGET_ESP32C3
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comment "ESP32-C6 is Slave Target from Wi-Fi Remote Component"
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depends on SLAVE_IDF_TARGET_ESP32C6
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comment "ESP32-C5 is Slave Target from Wi-Fi Remote Component"
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depends on SLAVE_IDF_TARGET_ESP32C5
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comment "ESP32-C61 is Slave Target from Wi-Fi Remote Component"
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depends on SLAVE_IDF_TARGET_ESP32C61
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# y if SDIO Transport is available, based on host and slave selection
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config ESP_HOSTED_PRIV_SDIO_OPTION
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bool
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default y if (IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4) && (SLAVE_IDF_TARGET_ESP32 || SLAVE_IDF_TARGET_ESP32C6 || SLAVE_IDF_TARGET_ESP32C5)
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default n
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# y if SPI HD Transport is available, based on host and slave selection
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config ESP_HOSTED_PRIV_SPI_HD_OPTION
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bool
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default n if (IDF_TARGET_ESP32 || SLAVE_IDF_TARGET_ESP32)
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default y
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choice ESP_HOSTED_HOST_INTERFACE
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bool "Transport layer"
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default ESP_HOSTED_SDIO_HOST_INTERFACE if ESP_HOSTED_PRIV_SDIO_OPTION
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default ESP_HOSTED_SPI_HOST_INTERFACE
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help
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Bus interface to be used for communication with the host
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config ESP_HOSTED_SPI_HOST_INTERFACE
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bool "SPI Full-duplex"
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help
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Enable/Disable SPI Full-duplex host interface
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config ESP_HOSTED_SDIO_HOST_INTERFACE
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depends on ESP_HOSTED_PRIV_SDIO_OPTION
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bool "SDIO"
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help
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Enable/Disable SDIO host interface
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# SPI Half Duplex is not supported in ESP32
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config ESP_HOSTED_SPI_HD_HOST_INTERFACE
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depends on ESP_HOSTED_PRIV_SPI_HD_OPTION
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bool "SPI Half-duplex"
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help
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Enable/Disable SPI Half-duplex host interface
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config ESP_HOSTED_UART_HOST_INTERFACE
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bool "UART"
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help
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Enable/Disable UART host interface
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endchoice
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config ESP_HOSTED_IDF_SLAVE_TARGET
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string
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default "esp32" if SLAVE_IDF_TARGET_ESP32
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default "esp32s2" if SLAVE_IDF_TARGET_ESP32S2
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default "esp32s3" if SLAVE_IDF_TARGET_ESP32S3
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default "esp32c2" if SLAVE_IDF_TARGET_ESP32C2
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default "esp32c3" if SLAVE_IDF_TARGET_ESP32C3
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default "esp32c6" if SLAVE_IDF_TARGET_ESP32C6
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default "esp32c5" if SLAVE_IDF_TARGET_ESP32C5
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default "invalid"
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menu "SPI Configuration"
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depends on ESP_HOSTED_SPI_HOST_INTERFACE
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choice ESP_HOSTED_SPI_PRIV_MODE_ESP32
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depends on SLAVE_IDF_TARGET_ESP32
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bool "Host SPI mode"
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default ESP_HOSTED_SPI_PRIV_MODE_2_ESP32
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config ESP_HOSTED_SPI_PRIV_MODE_0_ESP32
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bool "Host SPI mode 0"
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config ESP_HOSTED_SPI_PRIV_MODE_1_ESP32
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bool "Host SPI mode 1"
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config ESP_HOSTED_SPI_PRIV_MODE_2_ESP32
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bool "Host SPI mode 2"
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config ESP_HOSTED_SPI_PRIV_MODE_3_ESP32
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bool "Host SPI mode 3"
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endchoice
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choice ESP_HOSTED_SPI_PRIV_MODE_ESP32XX
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depends on !SLAVE_IDF_TARGET_ESP32
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bool "Host SPI mode"
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default ESP_HOSTED_SPI_PRIV_MODE_3_ESP32XX
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config ESP_HOSTED_SPI_PRIV_MODE_0_ESP32XX
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bool "Host SPI mode 0"
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config ESP_HOSTED_SPI_PRIV_MODE_1_ESP32XX
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bool "Host SPI mode 1"
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config ESP_HOSTED_SPI_PRIV_MODE_2_ESP32XX
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bool "Host SPI mode 2"
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config ESP_HOSTED_SPI_PRIV_MODE_3_ESP32XX
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bool "Host SPI mode 3"
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endchoice
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config ESP_HOSTED_SPI_MODE
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int
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default 0 if ESP_HOSTED_SPI_PRIV_MODE_0_ESP32
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default 1 if ESP_HOSTED_SPI_PRIV_MODE_1_ESP32
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default 2 if ESP_HOSTED_SPI_PRIV_MODE_2_ESP32
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default 3 if ESP_HOSTED_SPI_PRIV_MODE_3_ESP32
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default 0 if ESP_HOSTED_SPI_PRIV_MODE_0_ESP32XX
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default 1 if ESP_HOSTED_SPI_PRIV_MODE_1_ESP32XX
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default 2 if ESP_HOSTED_SPI_PRIV_MODE_2_ESP32XX
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default 3 if ESP_HOSTED_SPI_PRIV_MODE_3_ESP32XX
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choice ESP_HOSTED_SPI_CONTROLLER
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bool "Host SPI controller to use"
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default ESP_HOSTED_SPI_HSPI
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config ESP_HOSTED_SPI_HSPI
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bool "HSPI/FSPI"
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help
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"HSPI/FSPI: SPI_controller_1"
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config ESP_HOSTED_SPI_VSPI
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depends on IDF_TARGET_ESP32
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bool "VSPI"
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help
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"VSPI: SPI_controller_2"
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endchoice
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config ESP_HOSTED_SPI_CONTROLLER
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int
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default 2 if ESP_HOSTED_SPI_VSPI
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default 1
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menu "Host SPI GPIOs Config"
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choice ESP_HOSTED_SPI_HANDSHAKE_GPIO_CONFIG
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bool "Handshake GPIO Config"
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default ESP_HOSTED_HS_ACTIVE_HIGH
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config ESP_HOSTED_HS_ACTIVE_HIGH
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bool "HS: Active High"
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config ESP_HOSTED_HS_ACTIVE_LOW
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bool "HS: Active Low"
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endchoice
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choice ESP_HOSTED_SPI_DATAREADY__GPIO_CONFIG
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bool "DataReady GPIO Config"
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default ESP_HOSTED_DR_ACTIVE_HIGH
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config ESP_HOSTED_DR_ACTIVE_HIGH
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bool "DR: Active High"
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config ESP_HOSTED_DR_ACTIVE_LOW
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bool "DR: Active Low"
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endchoice
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choice ESP_HOSTED_SPI_RESET_GPIO_CONFIG
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bool "Reset GPIO Config"
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default ESP_HOSTED_SPI_RESET_ACTIVE_HIGH
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help
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"If Active High, High->Low->High will trigger reset (Low will trigger reset)
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If Active Low, Low->High->Low will trigger reset (High will trigger reset)"
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config ESP_HOSTED_SPI_RESET_ACTIVE_HIGH
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bool "RESET: Active High"
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config ESP_HOSTED_SPI_RESET_ACTIVE_LOW
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bool "RESET: Active Low"
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endchoice
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config ESP_HOSTED_SPI_HSPI_GPIO_MOSI
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depends on ESP_HOSTED_SPI_HSPI
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int "GPIO pin for Host MOSI"
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default 14 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
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default 23 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
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default 13 if IDF_TARGET_ESP32
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default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
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default 5 if IDF_TARGET_ESP32H2
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default 7
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help
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SPI controller Host MOSI
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config ESP_HOSTED_SPI_HSPI_GPIO_MISO
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depends on ESP_HOSTED_SPI_HSPI
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int "GPIO pin for Host MISO"
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default 15 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
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default 22 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
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default 12 if IDF_TARGET_ESP32
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default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
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default 0 if IDF_TARGET_ESP32H2
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default 2
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help
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SPI controller Host MISO
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config ESP_HOSTED_SPI_HSPI_GPIO_CLK
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depends on ESP_HOSTED_SPI_HSPI
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int "GPIO pin for Host CLK"
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default 18 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
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default 33 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
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default 14 if IDF_TARGET_ESP32
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default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
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default 4 if IDF_TARGET_ESP32H2
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default 6
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help
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SPI controller Host CLK
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config ESP_HOSTED_SPI_HSPI_GPIO_CS
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depends on ESP_HOSTED_SPI_HSPI
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int "GPIO pin for Host CS"
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default 19 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
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default 4 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
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default 15 if IDF_TARGET_ESP32
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default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
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default 1 if IDF_TARGET_ESP32H2
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default 10
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help
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SPI controller Host CS
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config ESP_HOSTED_SPI_VSPI_GPIO_MOSI
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depends on ESP_HOSTED_SPI_VSPI
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int "GPIO pin for Host MOSI"
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default 23
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help
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SPI controller Host MOSI
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config ESP_HOSTED_SPI_VSPI_GPIO_MISO
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depends on ESP_HOSTED_SPI_VSPI
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int "GPIO pin for Host MISO"
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default 19
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help
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SPI controller Host MISO
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config ESP_HOSTED_SPI_VSPI_GPIO_CLK
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depends on ESP_HOSTED_SPI_VSPI
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int "GPIO pin for Host CLK"
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default 18
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help
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SPI controller Host CLK
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config ESP_HOSTED_SPI_VSPI_GPIO_CS
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depends on ESP_HOSTED_SPI_VSPI
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int "GPIO pin for Host CS"
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default 5
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help
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SPI controller Host CS
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config ESP_HOSTED_SPI_GPIO_MOSI
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int
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default ESP_HOSTED_SPI_VSPI_GPIO_MOSI if ESP_HOSTED_SPI_VSPI
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default ESP_HOSTED_SPI_HSPI_GPIO_MOSI
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config ESP_HOSTED_SPI_GPIO_MISO
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int
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default ESP_HOSTED_SPI_VSPI_GPIO_MISO if ESP_HOSTED_SPI_VSPI
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default ESP_HOSTED_SPI_HSPI_GPIO_MISO
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config ESP_HOSTED_SPI_GPIO_CLK
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int
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default ESP_HOSTED_SPI_VSPI_GPIO_CLK if ESP_HOSTED_SPI_VSPI
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default ESP_HOSTED_SPI_HSPI_GPIO_CLK
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config ESP_HOSTED_SPI_GPIO_CS
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int
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default ESP_HOSTED_SPI_VSPI_GPIO_CS if ESP_HOSTED_SPI_VSPI
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default ESP_HOSTED_SPI_HSPI_GPIO_CS
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config ESP_HOSTED_SPI_GPIO_HANDSHAKE
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int "GPIO pin for handshake"
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default 16 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
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default 21 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
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default 3 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6
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default 17 if IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32S2
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default 22 if IDF_TARGET_ESP32H2
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default 26
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help
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GPIO pin to use for handshake with other spi controller
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config ESP_HOSTED_SPI_GPIO_DATA_READY
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int "GPIO pin for data ready interrupt"
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default 17 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
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default 32 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
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default 12 if IDF_TARGET_ESP32H2
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default 4
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help
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GPIO pin for indicating host that SPI slave has data to be read by host
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config ESP_HOSTED_SPI_GPIO_RESET_SLAVE
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int "GPIO pin for Reseting slave ESP"
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default 54 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
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default 53 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
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default 10 if IDF_TARGET_ESP32H2
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default 5
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help
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GPIO pin for Resetting ESP SPI slave device. Should be connected to RST/EN of ESP SPI slave device.
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endmenu
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ESP32XX_SPI_CLK_FREQ_RANGE_MIN := 1
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ESP32_SPI_CLK_FREQ_RANGE_MAX := 10
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ESP32C6_SPI_CLK_FREQ_RANGE_MAX := 40
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ESP32XX_SPI_CLK_FREQ_RANGE_MAX := 40
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config ESP_HOSTED_SPI_FREQ_ESP32
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depends on SLAVE_IDF_TARGET_ESP32
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int "SPI Clock Freq (MHz)"
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default 10
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range $(ESP32XX_SPI_CLK_FREQ_RANGE_MIN) $(ESP32_SPI_CLK_FREQ_RANGE_MAX)
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help
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"Optimize SPI CLK by increasing till host practically can support"
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config ESP_HOSTED_SPI_FREQ_ESP32C6
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depends on SLAVE_IDF_TARGET_ESP32C6
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int "SPI Clock Freq (MHz)"
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default 40 if IDF_TARGET_ESP32P4 #config for ESP32-P4 Function_EV_Board
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default 26
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range $(ESP32XX_SPI_CLK_FREQ_RANGE_MIN) $(ESP32C6_SPI_CLK_FREQ_RANGE_MAX)
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help
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"Optimize SPI CLK by increasing till host practically can support"
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config ESP_HOSTED_SPI_FREQ_ESP32XX
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depends on SLAVE_IDF_TARGET_ESP32C2 || SLAVE_IDF_TARGET_ESP32C3 || SLAVE_IDF_TARGET_ESP32S2 || SLAVE_IDF_TARGET_ESP32S3 || SLAVE_IDF_TARGET_ESP32C5
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int "SPI Clock Freq"
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default 40 if SLAVE_IDF_TARGET_ESP32C2 || SLAVE_IDF_TARGET_ESP32C3 || SLAVE_IDF_TARGET_ESP32S2 || SLAVE_IDF_TARGET_ESP32S3 || SLAVE_IDF_TARGET_ESP32C5
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range $(ESP32XX_SPI_CLK_FREQ_RANGE_MIN) $(ESP32XX_SPI_CLK_FREQ_RANGE_MAX)
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help
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"Optimize SPI CLK by increasing till host practically can support"
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config ESP_HOSTED_SPI_CLK_FREQ
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int
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default ESP_HOSTED_SPI_FREQ_ESP32 if SLAVE_IDF_TARGET_ESP32
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default ESP_HOSTED_SPI_FREQ_ESP32C6 if SLAVE_IDF_TARGET_ESP32C6
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default ESP_HOSTED_SPI_FREQ_ESP32XX if SLAVE_IDF_TARGET_ESP32C2 || SLAVE_IDF_TARGET_ESP32C3 || SLAVE_IDF_TARGET_ESP32S2 || SLAVE_IDF_TARGET_ESP32S3 || SLAVE_IDF_TARGET_ESP32C5
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help
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"Optimize SPI CLK by increasing till host practically can support"
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config ESP_HOSTED_SPI_TX_Q_SIZE
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int "ESP to Host SPI queue size"
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default 20
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help
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Very small tx queue will lower ESP -- SPI --> Host data rate
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config ESP_HOSTED_SPI_RX_Q_SIZE
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int "Host to ESP SPI queue size"
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default 20
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help
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Very small RX queue will lower ESP <-- SPI -- Host data rate
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endmenu
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menu "Hosted SDIO Configuration"
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depends on ESP_HOSTED_SDIO_HOST_INTERFACE
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choice ESP_HOSTED_SDIO_RESET_GPIO_CONFIG
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bool "RESET GPIO Config"
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default ESP_HOSTED_SDIO_RESET_ACTIVE_HIGH
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help
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"If Active High, High->Low->High will trigger reset (Low will trigger reset)
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If Active Low, Low->High->Low will trigger reset (High will trigger reset)"
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config ESP_HOSTED_SDIO_RESET_ACTIVE_HIGH
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bool "RESET: Active High"
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config ESP_HOSTED_SDIO_RESET_ACTIVE_LOW
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bool "RESET: Active Low"
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endchoice
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choice ESP_HOSTED_SDIO_RX_OPTIMIZATION
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bool "SDIO Receive Optimization"
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default ESP_HOSTED_SDIO_OPTIMIZATION_RX_STREAMING_MODE
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config ESP_HOSTED_SDIO_OPTIMIZATION_RX_NONE
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bool "No optimization"
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help
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Use SDIO as is, with no optimizations.
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config ESP_HOSTED_SDIO_OPTIMIZATION_RX_MAX_SIZE
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bool "Always Rx Max Packet size"
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help
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Always read max Rx Packet Size (512 * 3 bytes). This saves one SDIO
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transaction (get Rx Packet Size) when reading data from slave by
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always transferring a fixed amount of data. Extra data at end of valid
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packet data is discarded.
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config ESP_HOSTED_SDIO_OPTIMIZATION_RX_STREAMING_MODE
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bool "Use Streaming Mode"
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help
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Receive a stream of queued data from the slave, made up of one or more
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packets of data. Host extracts packets from the stream. This improves
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SDIO read performance by doing one large read transaction instead of
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many smaller read transactions for each packet.
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(Note: requires slave to support streaming mode.)
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endchoice
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choice
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prompt "SDIO Slot To Use"
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default ESP_HOSTED_SDIO_SLOT_1
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help
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On the ESP32-P4 EV Board:
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- Slot 0 connects to the MicroSD Card slot
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- Slot 1 connects to the on-board ESP32-C6
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For the ESP32, Slot 0 is usually occupied by SPI Flash and not usable for SDIO.
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For the ESP32-P4, Slot 0 is IOMUXed and GPIO values cannot be changed
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config ESP_HOSTED_SDIO_SLOT_0
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depends on IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32S3
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bool "Slot 0"
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config ESP_HOSTED_SDIO_SLOT_1
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bool "Slot 1"
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endchoice
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config ESP_HOSTED_SDIO_SLOT
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int
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default 0 if ESP_HOSTED_SDIO_SLOT_0
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default 1 if ESP_HOSTED_SDIO_SLOT_1
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config ESP_HOSTED_SD_PWR_CTRL_LDO_INTERNAL_IO
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depends on SOC_SDMMC_IO_POWER_EXTERNAL
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bool "SDIO power supply comes from internal LDO IO (READ HELP!)"
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default n
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help
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Only needed when the SDIO module is connected to specific IO pins which can be used for high-speed SDIO.
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Please read the schematic first and check if the SD VDD is connected to any internal LDO output.
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Unselect this option if the SDIO is powered by an external power supply.
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For ESP32-P4 EV Board, SDMMC slot 0 may require internal LDO output.
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config ESP_HOSTED_SD_PWR_CTRL_LDO_IO_ID
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depends on SOC_SDMMC_IO_POWER_EXTERNAL && ESP_HOSTED_SD_PWR_CTRL_LDO_INTERNAL_IO
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int "LDO ID"
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default 4 if IDF_TARGET_ESP32P4
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help
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Please check your schematic first and input your LDO ID.
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choice
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prompt "SDIO Bus Width"
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default ESP_HOSTED_SDIO_4_BIT_BUS
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help
|
|
Select the SDIO Bus Width to use
|
|
|
|
config ESP_HOSTED_SDIO_4_BIT_BUS
|
|
bool "4 Bits"
|
|
|
|
config ESP_HOSTED_SDIO_1_BIT_BUS
|
|
bool "1 Bit"
|
|
endchoice
|
|
|
|
config ESP_HOSTED_SDIO_BUS_WIDTH
|
|
int
|
|
default 1 if ESP_HOSTED_SDIO_1_BIT_BUS
|
|
default 4
|
|
|
|
ESP32_SDIO_CLK_FREQ_KHZ_RANGE_MIN := 400
|
|
ESP32_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 40000
|
|
ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MIN := 400
|
|
ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 50000
|
|
|
|
config ESP_HOSTED_SDIO_CLOCK_FREQ_KHZ
|
|
int "SDIO Clock Freq (in kHz)"
|
|
default 40000
|
|
range $(ESP32_SDIO_CLK_FREQ_KHZ_RANGE_MIN) $(ESP32_SDIO_CLK_FREQ_KHZ_RANGE_MAX) if IDF_TARGET_ESP32
|
|
range $(ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MIN) $(ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MAX) if IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4
|
|
help
|
|
"Optimize SDIO CLK by increasing till host practically can support. Clock frequency for ESP32-P4 as host <= 40MHz"
|
|
|
|
config ESP_HOSTED_CUSTOM_SDIO_PINS
|
|
bool "Use custom SDIO GPIO pins"
|
|
default n
|
|
help
|
|
Enable this to use custom GPIO pins for SDIO on ESP32-P4 and ESP32-S3.
|
|
ESP32 has fixed GPIOs for SDIO host (Do not use custom GPIOs)
|
|
ESP32-P4 slot 0 is fixed GPIOs for SDIO host (Do not use custom GPIOs)
|
|
ESP32-P4 slot 1, ESP32-S3 slot 0/1 is flexible GPIOs for SDIO host (Flexible GPIOs)
|
|
|
|
config ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MIN
|
|
int
|
|
default 4 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 19 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 15 if IDF_TARGET_ESP32
|
|
default 0
|
|
|
|
config ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MAX
|
|
int
|
|
default 4 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 19 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 15 if IDF_TARGET_ESP32
|
|
default 100
|
|
|
|
config ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MIN
|
|
int
|
|
default 33 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 18 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 14 if IDF_TARGET_ESP32
|
|
default 0
|
|
|
|
config ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MAX
|
|
int
|
|
default 33 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 18 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 14 if IDF_TARGET_ESP32
|
|
default 100
|
|
|
|
config ESP_HOSTED_SDIO_D0_GPIO_RANGE_MIN
|
|
int
|
|
default 20 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 14 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 2 if IDF_TARGET_ESP32
|
|
default 0
|
|
|
|
config ESP_HOSTED_SDIO_D0_GPIO_RANGE_MAX
|
|
int
|
|
default 20 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 14 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 2 if IDF_TARGET_ESP32
|
|
default 100
|
|
|
|
config ESP_HOSTED_SDIO_D1_GPIO_RANGE_MIN
|
|
int
|
|
default 23 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 15 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 4 if IDF_TARGET_ESP32
|
|
default 0
|
|
|
|
config ESP_HOSTED_SDIO_D1_GPIO_RANGE_MAX
|
|
int
|
|
default 23 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 15 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 4 if IDF_TARGET_ESP32
|
|
default 100
|
|
|
|
config ESP_HOSTED_SDIO_D2_GPIO_RANGE_MIN
|
|
int
|
|
default 21 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 16 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 12 if IDF_TARGET_ESP32
|
|
default 0
|
|
|
|
config ESP_HOSTED_SDIO_D2_GPIO_RANGE_MAX
|
|
int
|
|
default 21 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 16 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 12 if IDF_TARGET_ESP32
|
|
default 100
|
|
|
|
config ESP_HOSTED_SDIO_D3_GPIO_RANGE_MIN
|
|
int
|
|
default 22 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 17 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 13 if IDF_TARGET_ESP32
|
|
default 0
|
|
|
|
config ESP_HOSTED_SDIO_D3_GPIO_RANGE_MAX
|
|
int
|
|
default 22 if !ESP_HOSTED_CUSTOM_SDIO_PINS && SLAVE_IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32P4
|
|
default 17 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 13 if IDF_TARGET_ESP32
|
|
default 100
|
|
|
|
config ESP_HOSTED_SDIO_RESET_SLAVE_GPIO_MIN
|
|
int
|
|
default 53 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 54 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 42 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32S3
|
|
default 5 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32
|
|
default 0
|
|
help
|
|
GPIO pin for Resetting ESP SDIO slave device. Should be connected to RST/EN of ESP SDIO slave device.
|
|
|
|
config ESP_HOSTED_SDIO_RESET_SLAVE_GPIO_MAX
|
|
int
|
|
default 53 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 54 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32P4
|
|
default 42 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32S3
|
|
default 5 if !ESP_HOSTED_CUSTOM_SDIO_PINS && IDF_TARGET_ESP32
|
|
default 100
|
|
|
|
### *START* GPIO SDIO pin configurations for Slot 0 and 1
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_CMD_SLOT_0
|
|
depends on ESP_HOSTED_SDIO_SLOT_0
|
|
int "CMD GPIO number"
|
|
default 47 if IDF_TARGET_ESP32S3
|
|
range 44 44 if IDF_TARGET_ESP32P4
|
|
range 15 15 if IDF_TARGET_ESP32
|
|
help
|
|
"Value can only be configured for some targets. Displayed always for reference."
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_CMD_SLOT_1
|
|
depends on ESP_HOSTED_SDIO_SLOT_1
|
|
int "CMD GPIO number"
|
|
default 47 if IDF_TARGET_ESP32S3
|
|
default 4 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 19 if IDF_TARGET_ESP32P4
|
|
default 15 if IDF_TARGET_ESP32
|
|
range ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MIN ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MAX
|
|
help
|
|
CMD GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
|
|
Enable 'Use custom SDIO GPIO pins' to disable range restrictions.
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_CLK_SLOT_0
|
|
depends on ESP_HOSTED_SDIO_SLOT_0
|
|
int "CLK GPIO number"
|
|
default 19 if IDF_TARGET_ESP32S3
|
|
range 43 43 if IDF_TARGET_ESP32P4
|
|
range 14 14 if IDF_TARGET_ESP32
|
|
help
|
|
"Value can only be configured for some targets. Displayed always for reference."
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_CLK_SLOT_1
|
|
depends on ESP_HOSTED_SDIO_SLOT_1
|
|
int "CLK GPIO number"
|
|
default 19 if IDF_TARGET_ESP32S3
|
|
default 33 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 18 if IDF_TARGET_ESP32P4
|
|
default 14 if IDF_TARGET_ESP32
|
|
range ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MIN ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MAX
|
|
help
|
|
CLK GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
|
|
Enable 'Use custom SDIO GPIO pins' to disable range restrictions.
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D0_SLOT_0
|
|
depends on ESP_HOSTED_SDIO_SLOT_0
|
|
int "D0 GPIO number"
|
|
default 13 if IDF_TARGET_ESP32S3
|
|
range 39 39 if IDF_TARGET_ESP32P4
|
|
range 2 2 if IDF_TARGET_ESP32
|
|
help
|
|
"Value can only be configured for some targets. Displayed always for reference."
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D0_SLOT_1
|
|
depends on ESP_HOSTED_SDIO_SLOT_1
|
|
int "D0 GPIO number"
|
|
default 13 if IDF_TARGET_ESP32S3
|
|
default 20 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 14 if IDF_TARGET_ESP32P4
|
|
default 2 if IDF_TARGET_ESP32
|
|
range ESP_HOSTED_SDIO_D0_GPIO_RANGE_MIN ESP_HOSTED_SDIO_D0_GPIO_RANGE_MAX
|
|
help
|
|
D0 GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
|
|
Enable 'Use custom SDIO GPIO pins' to disable range restrictions.
|
|
|
|
if ESP_HOSTED_SDIO_4_BIT_BUS
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D1_4BIT_BUS_SLOT_0
|
|
depends on ESP_HOSTED_SDIO_SLOT_0
|
|
int "D1 GPIO number"
|
|
default 35 if IDF_TARGET_ESP32S3
|
|
range 40 40 if IDF_TARGET_ESP32P4
|
|
range 4 4 if IDF_TARGET_ESP32
|
|
help
|
|
"Value can only be configured for some targets. Displayed always for reference."
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D1_4BIT_BUS_SLOT_1
|
|
depends on ESP_HOSTED_SDIO_SLOT_1
|
|
int "D1 GPIO number"
|
|
default 35 if IDF_TARGET_ESP32S3
|
|
default 23 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 15 if IDF_TARGET_ESP32P4
|
|
default 4 if IDF_TARGET_ESP32
|
|
range ESP_HOSTED_SDIO_D1_GPIO_RANGE_MIN ESP_HOSTED_SDIO_D1_GPIO_RANGE_MAX
|
|
help
|
|
D1 GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
|
|
Enable 'Use custom SDIO GPIO pins' to disable range restrictions.
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D2_4BIT_BUS_SLOT_0
|
|
depends on ESP_HOSTED_SDIO_SLOT_0
|
|
int "D2 GPIO number"
|
|
default 20 if IDF_TARGET_ESP32S3
|
|
range 41 41 if IDF_TARGET_ESP32P4
|
|
range 12 12 if IDF_TARGET_ESP32
|
|
help
|
|
"Value can only be configured for some targets. Displayed always for reference."
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D2_4BIT_BUS_SLOT_1
|
|
depends on ESP_HOSTED_SDIO_SLOT_1
|
|
int "D2 GPIO number"
|
|
default 20 if IDF_TARGET_ESP32S3
|
|
default 21 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 16 if IDF_TARGET_ESP32P4
|
|
default 12 if IDF_TARGET_ESP32
|
|
range ESP_HOSTED_SDIO_D2_GPIO_RANGE_MIN ESP_HOSTED_SDIO_D2_GPIO_RANGE_MAX
|
|
help
|
|
D2 GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
|
|
Enable 'Use custom SDIO GPIO pins' to disable range restrictions.
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D3_4BIT_BUS_SLOT_0
|
|
depends on ESP_HOSTED_SDIO_SLOT_0
|
|
int "D3 GPIO number"
|
|
default 9 if IDF_TARGET_ESP32S3
|
|
range 42 42 if IDF_TARGET_ESP32P4
|
|
range 13 13 if IDF_TARGET_ESP32
|
|
help
|
|
"Value can only be configured for some targets. Displayed always for reference."
|
|
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D3_4BIT_BUS_SLOT_1
|
|
depends on ESP_HOSTED_SDIO_SLOT_1
|
|
int "D3 GPIO number"
|
|
default 9 if IDF_TARGET_ESP32S3
|
|
default 22 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 17 if IDF_TARGET_ESP32P4
|
|
default 13 if IDF_TARGET_ESP32
|
|
range ESP_HOSTED_SDIO_D3_GPIO_RANGE_MIN ESP_HOSTED_SDIO_D3_GPIO_RANGE_MAX
|
|
help
|
|
D3 GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
|
|
Enable 'Use custom SDIO GPIO pins' to disable range restrictions.
|
|
endif
|
|
|
|
if !ESP_HOSTED_SDIO_4_BIT_BUS
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D1_1BIT_BUS_SLOT_0
|
|
depends on ESP_HOSTED_SDIO_SLOT_0
|
|
int "D1 GPIO number (Interrupt Line)"
|
|
default 35 if IDF_TARGET_ESP32S3
|
|
range 40 40 if IDF_TARGET_ESP32P4
|
|
range 4 4 if IDF_TARGET_ESP32
|
|
help
|
|
"Value can only be configured for some targets. Displayed always for reference."
|
|
config ESP_HOSTED_PRIV_SDIO_PIN_D1_1BIT_BUS_SLOT_1
|
|
depends on ESP_HOSTED_SDIO_SLOT_1
|
|
int "D1 GPIO number (Interrupt Line)"
|
|
default 35 if IDF_TARGET_ESP32S3
|
|
default 23 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 15 if IDF_TARGET_ESP32P4
|
|
default 4 if IDF_TARGET_ESP32
|
|
range ESP_HOSTED_SDIO_D1_GPIO_RANGE_MIN ESP_HOSTED_SDIO_D1_GPIO_RANGE_MAX
|
|
help
|
|
D1 GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
|
|
Enable 'Use custom SDIO GPIO pins' to disable range restrictions.
|
|
endif
|
|
|
|
config ESP_HOSTED_SDIO_GPIO_RESET_SLAVE
|
|
int "GPIO pin for Reseting slave ESP"
|
|
range ESP_HOSTED_SDIO_RESET_SLAVE_GPIO_MIN ESP_HOSTED_SDIO_RESET_SLAVE_GPIO_MAX
|
|
default 53 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 54 if IDF_TARGET_ESP32P4
|
|
default 42 if IDF_TARGET_ESP32S3
|
|
default 5 if IDF_TARGET_ESP32
|
|
help
|
|
GPIO pin for Resetting ESP SDIO slave device. Should be connected to RST/EN of ESP SDIO slave device.
|
|
|
|
### *END* GPIO SDIO pin configurations for Slot 0 and 1
|
|
|
|
config ESP_HOSTED_SDIO_PIN_CMD
|
|
int
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_CMD_SLOT_0 if ESP_HOSTED_SDIO_SLOT_0
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_CMD_SLOT_1 if ESP_HOSTED_SDIO_SLOT_1
|
|
|
|
config ESP_HOSTED_SDIO_PIN_CLK
|
|
int
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_CLK_SLOT_0 if ESP_HOSTED_SDIO_SLOT_0
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_CLK_SLOT_1 if ESP_HOSTED_SDIO_SLOT_1
|
|
|
|
config ESP_HOSTED_SDIO_PIN_D0
|
|
int
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D0_SLOT_0 if ESP_HOSTED_SDIO_SLOT_0
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D0_SLOT_1 if ESP_HOSTED_SDIO_SLOT_1
|
|
|
|
if ESP_HOSTED_SDIO_4_BIT_BUS
|
|
config ESP_HOSTED_SDIO_PRIV_PIN_D1_4BIT_BUS
|
|
int
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D1_4BIT_BUS_SLOT_0 if ESP_HOSTED_SDIO_SLOT_0
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D1_4BIT_BUS_SLOT_1 if ESP_HOSTED_SDIO_SLOT_1
|
|
|
|
config ESP_HOSTED_SDIO_PIN_D2
|
|
int
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D2_4BIT_BUS_SLOT_0 if ESP_HOSTED_SDIO_SLOT_0
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D2_4BIT_BUS_SLOT_1 if ESP_HOSTED_SDIO_SLOT_1
|
|
|
|
config ESP_HOSTED_SDIO_PIN_D3
|
|
int
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D3_4BIT_BUS_SLOT_0 if ESP_HOSTED_SDIO_SLOT_0
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D3_4BIT_BUS_SLOT_1 if ESP_HOSTED_SDIO_SLOT_1
|
|
endif
|
|
|
|
if !ESP_HOSTED_SDIO_4_BIT_BUS
|
|
config ESP_HOSTED_SDIO_PRIV_PIN_D1_1BIT_BUS
|
|
int
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D1_1BIT_BUS_SLOT_0 if ESP_HOSTED_SDIO_SLOT_0
|
|
default ESP_HOSTED_PRIV_SDIO_PIN_D1_1BIT_BUS_SLOT_1 if ESP_HOSTED_SDIO_SLOT_1
|
|
endif
|
|
|
|
config ESP_HOSTED_SDIO_PIN_D1
|
|
int
|
|
default ESP_HOSTED_SDIO_PRIV_PIN_D1_4BIT_BUS if ESP_HOSTED_SDIO_4_BIT_BUS
|
|
default ESP_HOSTED_SDIO_PRIV_PIN_D1_1BIT_BUS if !ESP_HOSTED_SDIO_4_BIT_BUS
|
|
|
|
config ESP_HOSTED_SDIO_TX_Q_SIZE
|
|
int "Host SDIO Tx queue size"
|
|
default 20
|
|
help
|
|
Very small tx queue will lower data rate
|
|
|
|
config ESP_HOSTED_SDIO_RX_Q_SIZE
|
|
int "Host SDIO Rx queue size"
|
|
default 20
|
|
help
|
|
Very small RX queue will lower data rate
|
|
|
|
config ESP_HOSTED_SDIO_CHECKSUM
|
|
bool "SDIO checksum ENABLE/DISABLE"
|
|
help
|
|
ENABLE/DISABLE software SDIO checksum
|
|
endmenu
|
|
|
|
menu "SPI Half-duplex Configuration"
|
|
depends on ESP_HOSTED_SPI_HD_HOST_INTERFACE
|
|
|
|
config ESP_HOSTED_SPI_HD_MODE
|
|
int "SPI Mode to use"
|
|
default 3
|
|
range 0 3
|
|
help
|
|
SPI Mode to use. The same mode must be used on both host and slave.
|
|
|
|
choice ESP_HOSTED_SPI_HD_PRIV_INTERFACE_NUM_DATA_LINES
|
|
bool "Num Data Lines to use"
|
|
default ESP_HOSTED_SPI_HD_PRIV_INTERFACE_4_DATA_LINES
|
|
help
|
|
Number of Data Lines to use in the SPI HD interface
|
|
|
|
config ESP_HOSTED_SPI_HD_PRIV_INTERFACE_4_DATA_LINES
|
|
bool "4 data lines"
|
|
|
|
config ESP_HOSTED_SPI_HD_PRIV_INTERFACE_2_DATA_LINES
|
|
bool "2 data lines"
|
|
endchoice
|
|
|
|
config ESP_HOSTED_SPI_HD_INTERFACE_NUM_DATA_LINES
|
|
int
|
|
default 4 if ESP_HOSTED_SPI_HD_PRIV_INTERFACE_4_DATA_LINES
|
|
default 2 if ESP_HOSTED_SPI_HD_PRIV_INTERFACE_2_DATA_LINES
|
|
|
|
choice ESP_HOSTED_SPI_HD_RESET_GPIO_CONFIG
|
|
bool "RESET GPIO Config"
|
|
default ESP_HOSTED_SPI_HD_RESET_ACTIVE_HIGH
|
|
help
|
|
"If Active High, High->Low->High will trigger reset (Low will trigger reset)
|
|
If Active Low, Low->High->Low will trigger reset (High will trigger reset)"
|
|
|
|
config ESP_HOSTED_SPI_HD_RESET_ACTIVE_HIGH
|
|
bool "RESET: Active High"
|
|
config ESP_HOSTED_SPI_HD_RESET_ACTIVE_LOW
|
|
bool "RESET: Active Low"
|
|
endchoice
|
|
|
|
choice ESP_HOSTED_SPI_HD_DATAREADY_GPIO_CONFIG
|
|
bool "DataReady GPIO Config"
|
|
default ESP_HOSTED_SPI_HD_DR_ACTIVE_HIGH
|
|
|
|
config ESP_HOSTED_SPI_HD_DR_ACTIVE_HIGH
|
|
bool "DR: Active High"
|
|
config ESP_HOSTED_SPI_HD_DR_ACTIVE_LOW
|
|
bool "DR: Active Low"
|
|
endchoice
|
|
|
|
menu "Host GPIOs Config"
|
|
config ESP_HOSTED_SPI_HD_GPIO_CS
|
|
int "GPIO pin for Host CS"
|
|
default 10 if IDF_TARGET_ESP32S3
|
|
default 4 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 19 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
|
|
default 1 if IDF_TARGET_ESP32H2
|
|
default 15
|
|
help
|
|
SPI Half-duplex controller Host CS
|
|
|
|
config ESP_HOSTED_SPI_HD_GPIO_CLK
|
|
int "GPIO pin for Host CLK"
|
|
default 12 if IDF_TARGET_ESP32S3
|
|
default 33 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 18 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
|
|
default 4 if IDF_TARGET_ESP32H2
|
|
default 18
|
|
help
|
|
SPI Half-duplex controller Host CLK
|
|
|
|
config ESP_HOSTED_SPI_HD_GPIO_D0
|
|
int "GPIO pin for Host D0"
|
|
default 11 if IDF_TARGET_ESP32S3
|
|
default 23 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 14 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
|
|
default 5 if IDF_TARGET_ESP32H2
|
|
default 2
|
|
help
|
|
SPI Half-duplex controller Host D0
|
|
|
|
config ESP_HOSTED_SPI_HD_GPIO_D1
|
|
int "GPIO pin for Host D1"
|
|
default 13 if IDF_TARGET_ESP32S3
|
|
default 22 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 15 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
|
|
default 0 if IDF_TARGET_ESP32H2
|
|
default 4
|
|
help
|
|
SPI Half-duplex controller Host D1
|
|
|
|
config ESP_HOSTED_SPI_HD_GPIO_D2
|
|
depends on ESP_HOSTED_SPI_HD_PRIV_INTERFACE_4_DATA_LINES
|
|
int "GPIO pin for Host D2"
|
|
default 14 if IDF_TARGET_ESP32S3
|
|
default 20 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 16 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
|
|
default 2 if IDF_TARGET_ESP32H2
|
|
default 12
|
|
help
|
|
SPI Half-duplex controller Host D2
|
|
|
|
config ESP_HOSTED_SPI_HD_GPIO_D3
|
|
depends on ESP_HOSTED_SPI_HD_PRIV_INTERFACE_4_DATA_LINES
|
|
int "GPIO pin for Host D3"
|
|
default 9 if IDF_TARGET_ESP32S3
|
|
default 21 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 17 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
|
|
default 3 if IDF_TARGET_ESP32H2
|
|
default 13
|
|
help
|
|
SPI Half-duplex controller Host D3
|
|
|
|
config ESP_HOSTED_SPI_HD_GPIO_DATA_READY
|
|
int "GPIO pin for data ready interrupt"
|
|
default 4 if IDF_TARGET_ESP32S3
|
|
default 32 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 6 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
|
|
default 12 if IDF_TARGET_ESP32H2
|
|
default 8
|
|
help
|
|
GPIO pin for indicating host that slave has data to be read by host
|
|
|
|
config ESP_HOSTED_SPI_HD_GPIO_RESET_SLAVE
|
|
int "GPIO pin for Reseting slave ESP"
|
|
default 5 if IDF_TARGET_ESP32S3
|
|
default 53 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C5
|
|
default 54 if IDF_TARGET_ESP32P4 && SLAVE_IDF_TARGET_ESP32C6
|
|
default 10 if IDF_TARGET_ESP32H2
|
|
default 5
|
|
help
|
|
GPIO pin for Resetting ESP slave device. Should be connected to RST/EN of ESP SPI slave device.
|
|
endmenu
|
|
|
|
ESP32XX_SPI_HD_CLK_FREQ_RANGE_MIN := 1
|
|
ESP32_SPI_HD_CLK_FREQ_RANGE_MAX := 10
|
|
ESP32C6_SPI_HD_CLK_FREQ_RANGE_MAX := 40
|
|
ESP32XX_SPI_HD_CLK_FREQ_RANGE_MAX := 40
|
|
|
|
config ESP_HOSTED_SPI_HD_FREQ_ESP32C6
|
|
depends on SLAVE_IDF_TARGET_ESP32C6
|
|
int "SPI HD Clock Freq (MHz)"
|
|
default 40 if IDF_TARGET_ESP32P4 #config for ESP32-P4 Function_EV_Board
|
|
default 10
|
|
range $(ESP32XX_SPI_HD_CLK_FREQ_RANGE_MIN) $(ESP32C6_SPI_HD_CLK_FREQ_RANGE_MAX)
|
|
help
|
|
"Optimize CLK by increasing till host practically can support"
|
|
|
|
config ESP_HOSTED_SPI_HD_FREQ_ESP32XX
|
|
depends on SLAVE_IDF_TARGET_ESP32C2 || SLAVE_IDF_TARGET_ESP32C3 || SLAVE_IDF_TARGET_ESP32S2 || SLAVE_IDF_TARGET_ESP32S3 || SLAVE_IDF_TARGET_ESP32C5
|
|
int "SPI HD Clock Freq (MHz)"
|
|
default 40 if SLAVE_IDF_TARGET_ESP32C2 || SLAVE_IDF_TARGET_ESP32C3 || SLAVE_IDF_TARGET_ESP32S2 || SLAVE_IDF_TARGET_ESP32S3 || SLAVE_IDF_TARGET_ESP32C5
|
|
range $(ESP32XX_SPI_HD_CLK_FREQ_RANGE_MIN) $(ESP32XX_SPI_HD_CLK_FREQ_RANGE_MAX)
|
|
help
|
|
"Optimize CLK by increasing till host practically can support"
|
|
|
|
config ESP_HOSTED_SPI_HD_CLK_FREQ
|
|
int
|
|
default ESP_HOSTED_SPI_HD_FREQ_ESP32C6 if SLAVE_IDF_TARGET_ESP32C6
|
|
default ESP_HOSTED_SPI_HD_FREQ_ESP32XX if SLAVE_IDF_TARGET_ESP32C2 || SLAVE_IDF_TARGET_ESP32C3 || SLAVE_IDF_TARGET_ESP32S2 || SLAVE_IDF_TARGET_ESP32S3 || SLAVE_IDF_TARGET_ESP32C5
|
|
help
|
|
"Optimize CLK by increasing till host practically can support"
|
|
|
|
config ESP_HOSTED_SPI_HD_TX_Q_SIZE
|
|
int "ESP to Host queue size"
|
|
default 20
|
|
help
|
|
Very small tx queue will lower ESP -- SPI Half-duplex --> Host data rate
|
|
|
|
config ESP_HOSTED_SPI_HD_RX_Q_SIZE
|
|
int "Host to ESP queue size"
|
|
default 20
|
|
help
|
|
Very small RX queue will lower ESP <-- SPI Half-duplex -- Host data rate
|
|
|
|
config ESP_HOSTED_SPI_HD_CHECKSUM
|
|
bool "Checksum ENABLE/DISABLE"
|
|
default y
|
|
help
|
|
ENABLE/DISABLE software checksum
|
|
endmenu
|
|
|
|
menu "UART Configuration"
|
|
depends on ESP_HOSTED_UART_HOST_INTERFACE
|
|
|
|
choice ESP_HOSTED_UART_RESET_GPIO_CONFIG
|
|
bool "RESET GPIO Config"
|
|
default ESP_HOSTED_UART_RESET_ACTIVE_HIGH
|
|
help
|
|
"If Active High, High->Low->High will trigger reset (Low will trigger reset)
|
|
If Active Low, Low->High->Low will trigger reset (High will trigger reset)"
|
|
|
|
config ESP_HOSTED_UART_RESET_ACTIVE_HIGH
|
|
bool "RESET: Active High"
|
|
config ESP_HOSTED_UART_RESET_ACTIVE_LOW
|
|
bool "RESET: Active Low"
|
|
endchoice
|
|
|
|
config ESP_HOSTED_UART_PORT
|
|
int "UART Port to Use"
|
|
default 1
|
|
range 0 2 if IDF_TARGET_ESP32
|
|
range 0 1 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C6
|
|
range 0 2 if IDF_TARGET_ESP32C61
|
|
range 0 1 if IDF_TARGET_ESP32S2
|
|
range 0 2 if IDF_TARGET_ESP32S3
|
|
range 0 4 if IDF_TARGET_ESP32P4
|
|
help
|
|
Select UART Port to Use. Do not select the UART Port used for console output (if enabled)
|
|
|
|
config ESP_HOSTED_UART_PIN_TX
|
|
int "TX GPIO number"
|
|
default 13 if IDF_TARGET_ESP32
|
|
default 5 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3
|
|
default 14 if IDF_TARGET_ESP32C5
|
|
default 21 if IDF_TARGET_ESP32C6
|
|
default 5 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
|
|
default 14 if IDF_TARGET_ESP32P4
|
|
help
|
|
GPIO used for UART TX
|
|
|
|
config ESP_HOSTED_UART_PIN_RX
|
|
int "RX GPIO number"
|
|
default 12 if IDF_TARGET_ESP32
|
|
default 4 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3
|
|
default 13 if IDF_TARGET_ESP32C5
|
|
default 20 if IDF_TARGET_ESP32C6
|
|
default 4 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
|
|
default 15 if IDF_TARGET_ESP32P4
|
|
help
|
|
GPIO used for UART RX
|
|
|
|
config ESP_HOSTED_UART_BAUDRATE
|
|
int "Baud Rate"
|
|
default 921600
|
|
range 9600 3500000
|
|
help
|
|
Baud Rate to Use. Make sure Hardware supports the rate. Standard rates are 9600, 19200, 38400, 57600, 115200, 460800, 921600
|
|
|
|
config ESP_HOSTED_UART_NUM_DATA_BITS
|
|
int "Number of Data Bits"
|
|
default 8
|
|
range 5 8
|
|
help
|
|
Number of Data Bits to use
|
|
|
|
choice ESP_HOSTED_UART_PRIV_PARITY
|
|
bool "Parity"
|
|
|
|
config ESP_HOSTED_UART_PRIV_PARITY_NONE
|
|
bool "None"
|
|
|
|
config ESP_HOSTED_UART_PRIV_PARITY_EVEN
|
|
bool "Even"
|
|
|
|
config ESP_HOSTED_UART_PRIV_PARITY_ODD
|
|
bool "Odd"
|
|
endchoice
|
|
|
|
config ESP_HOSTED_UART_PARITY
|
|
int
|
|
default 0 if ESP_HOSTED_UART_PRIV_PARITY_NONE
|
|
default 1 if ESP_HOSTED_UART_PRIV_PARITY_EVEN
|
|
default 2 if ESP_HOSTED_UART_PRIV_PARITY_ODD
|
|
|
|
choice ESP_HOSTED_UART_PRIV_STOP_BITS
|
|
bool "Number of Stop Bits"
|
|
|
|
config ESP_HOSTED_UART_PRIV_STOP_BITS_1
|
|
bool "1"
|
|
|
|
config ESP_HOSTED_UART_PRIV_STOP_BITS_1_5
|
|
bool "1.5"
|
|
|
|
config ESP_HOSTED_UART_PRIV_STOP_BITS_2
|
|
bool "2"
|
|
endchoice
|
|
|
|
config ESP_HOSTED_UART_STOP_BITS
|
|
int
|
|
default 0 if ESP_HOSTED_UART_PRIV_STOP_BITS_1
|
|
default 1 if ESP_HOSTED_UART_PRIV_STOP_BITS_1_5
|
|
default 2 if ESP_HOSTED_UART_PRIV_STOP_BITS_2
|
|
|
|
config ESP_HOSTED_UART_GPIO_RESET_SLAVE
|
|
int "GPIO pin for Reseting slave ESP"
|
|
default 54 if IDF_TARGET_ESP32P4
|
|
default 42 if IDF_TARGET_ESP32S3
|
|
default 5
|
|
help
|
|
GPIO pin for Resetting ESP SDIO slave device. Should be connected to RST/EN of ESP SDIO slave device.
|
|
|
|
config ESP_HOSTED_UART_TX_Q_SIZE
|
|
int "Tx Queue Size"
|
|
default 5
|
|
help
|
|
UART rates are low, so large queue sizes are not required
|
|
|
|
config ESP_HOSTED_UART_RX_Q_SIZE
|
|
int "Rx Queue Size"
|
|
default 5
|
|
help
|
|
UART rates are low, so large queue sizes are not required
|
|
|
|
config ESP_HOSTED_UART_CHECKSUM
|
|
bool "UART checksum ENABLE/DISABLE"
|
|
default y
|
|
help
|
|
ENABLE/DISABLE software UART checksum
|
|
endmenu
|
|
|
|
config ESP_HOSTED_GPIO_SLAVE_RESET_SLAVE
|
|
int
|
|
default ESP_HOSTED_SPI_GPIO_RESET_SLAVE if ESP_HOSTED_SPI_HOST_INTERFACE
|
|
default ESP_HOSTED_SDIO_GPIO_RESET_SLAVE if ESP_HOSTED_SDIO_HOST_INTERFACE
|
|
default ESP_HOSTED_SPI_HD_GPIO_RESET_SLAVE if ESP_HOSTED_SPI_HD_HOST_INTERFACE
|
|
default ESP_HOSTED_UART_GPIO_RESET_SLAVE if ESP_HOSTED_UART_HOST_INTERFACE
|
|
|
|
config ESP_HOSTED_RESET_GPIO_ACTIVE_LOW
|
|
bool
|
|
default n if ESP_HOSTED_SDIO_RESET_ACTIVE_HIGH || ESP_HOSTED_SPI_RESET_ACTIVE_HIGH || ESP_HOSTED_SPI_HD_RESET_ACTIVE_HIGH || ESP_HOSTED_UART_RESET_ACTIVE_HIGH
|
|
default y if ESP_HOSTED_SDIO_RESET_ACTIVE_LOW || ESP_HOSTED_SPI_RESET_ACTIVE_LOW || ESP_HOSTED_SPI_HD_RESET_ACTIVE_LOW || ESP_HOSTED_UART_RESET_ACTIVE_LOW
|
|
|
|
menu "Bluetooth Support"
|
|
|
|
comment "Following options must be set before this option can be enabled"
|
|
depends on !BT_ENABLED || BT_CONTROLLER_ONLY || (BT_NIMBLE_ENABLED && (BT_NIMBLE_TRANSPORT_UART || BT_CONTROLLER_ENABLED)) || (BT_BLUEDROID_ENABLED && BT_CONTROLLER_ENABLED)
|
|
|
|
comment "'Component config->Bluetooth' must be enabled"
|
|
depends on !BT_ENABLED
|
|
|
|
comment "'Component config->Bluetooth->Host' must be enabled"
|
|
depends on BT_ENABLED && BT_CONTROLLER_ONLY
|
|
|
|
comment "'Component config->Bluetooth->Controller' must be disabled"
|
|
depends on BT_ENABLED && BT_CONTROLLER_ENABLED
|
|
|
|
comment "'Component config->Bluetooth->NimBLE Options->Host-controller Transport->Uart Transport' must be disabled"
|
|
depends on BT_NIMBLE_ENABLED && BT_NIMBLE_TRANSPORT_UART
|
|
|
|
if BT_ENABLED && BT_BLUEDROID_ENABLED && !BT_CONTROLLER_ENABLED
|
|
config ESP_HOSTED_ENABLE_BT_BLUEDROID
|
|
bool "Enable Hosted Bluedroid Bluetooth support"
|
|
default n
|
|
help
|
|
Enable Bluetooth Support for Bluedroid via Hosted
|
|
|
|
choice ESP_HOSTED_BLUEDROID_HCI_TYPE
|
|
bool "BT Bluedroid HCI Type"
|
|
default ESP_HOSTED_BLUEDROID_HCI_VHCI
|
|
depends on ESP_HOSTED_ENABLE_BT_BLUEDROID
|
|
help
|
|
Selects the HCI to use
|
|
|
|
config ESP_HOSTED_BLUEDROID_HCI_VHCI
|
|
bool "VHCI"
|
|
help
|
|
Bluetooth data is sent through the selected transport layer
|
|
endchoice
|
|
endif
|
|
|
|
if BT_ENABLED && BT_NIMBLE_ENABLED && !BT_CONTROLLER_ENABLED && !BT_NIMBLE_TRANSPORT_UART
|
|
config ESP_HOSTED_ENABLE_BT_NIMBLE
|
|
bool "Enable Hosted Nimble Bluetooth support"
|
|
default n
|
|
help
|
|
Enable Bluetooth Support via Hosted
|
|
|
|
choice ESP_HOSTED_NIMBLE_HCI_TYPE
|
|
bool "BT Nimble HCI Type"
|
|
default ESP_HOSTED_NIMBLE_HCI_VHCI
|
|
depends on ESP_HOSTED_ENABLE_BT_NIMBLE
|
|
help
|
|
Selects the HCI to use
|
|
|
|
config ESP_HOSTED_NIMBLE_HCI_VHCI
|
|
bool "VHCI"
|
|
help
|
|
Bluetooth data is sent through the selected transport layer
|
|
endchoice
|
|
endif
|
|
endmenu
|
|
|
|
menu "Task defaults"
|
|
config ESP_HOSTED_RPC_TASK_STACK
|
|
int "RPC task stack size"
|
|
default 4096
|
|
|
|
config ESP_HOSTED_DFLT_TASK_STACK
|
|
int "Hosted default task size"
|
|
default 3072
|
|
endmenu
|
|
|
|
config ESP_HOSTED_USE_MEMPOOL
|
|
bool "Cache allocated memory like mempool - helps to reduce malloc calls"
|
|
default y
|
|
help
|
|
Cache allocated memory - reduces number of malloc calls
|
|
|
|
config ESP_HOSTED_MAX_SIMULTANEOUS_SYNC_RPC_REQUESTS
|
|
int "Maximum number of simultaneous synchronous RPC Request"
|
|
default 5
|
|
help
|
|
Sets the maximum number of simultaneous synchronous RPC Requests.
|
|
(Synchronous RPC Request: each sending task waits for the response.)
|
|
Usually, the host application may send up to 3 simultaneous RPC requests to the slave.
|
|
Increase this number if you need to send more simultaneous RPC requests.
|
|
Note: the slave will only process one RPC request (sync and async) at a time
|
|
|
|
config ESP_HOSTED_MAX_SIMULTANEOUS_ASYNC_RPC_REQUESTS
|
|
int "Maximum number of simultaneous asynchronous RPC Request"
|
|
default 5
|
|
help
|
|
Sets the maximum number of simultaneous asynchronous RPC Requests.
|
|
(Asynchronous RPC Request: each sending task registers a callback to get the response.)
|
|
Usually, the host application may send up to 3 simultaneous RPC requests to the slave.
|
|
Increase this number if you need to send more simultaneous RPC requests.
|
|
Note: the slave will only process one RPC request (sync and async) at a time
|
|
|
|
menu "Debug Settings"
|
|
|
|
config ESP_HOSTED_RAW_THROUGHPUT_TRANSPORT
|
|
bool "RawTP: Transport level throughput debug test"
|
|
default n
|
|
help
|
|
Find max transport performance which helps to assess stability of porting done
|
|
|
|
choice ESP_HOSTED_RAW_THROUGHPUT_DIRECTION
|
|
bool "RawTP: Send data from:"
|
|
depends on ESP_HOSTED_RAW_THROUGHPUT_TRANSPORT
|
|
|
|
config ESP_HOSTED_RAW_THROUGHPUT_TX_TO_SLAVE
|
|
bool "Host to Slave"
|
|
help
|
|
Sends data from Host to Slave
|
|
|
|
config ESP_HOSTED_RAW_THROUGHPUT_RX_FROM_SLAVE
|
|
bool "Slave to Host"
|
|
help
|
|
Sends data from Slave to Slave
|
|
|
|
config ESP_HOSTED_RAW_THROUGHPUT_BIDIRECTIONAL
|
|
bool "Bidirectional"
|
|
help
|
|
Sends data in both directions
|
|
endchoice
|
|
|
|
config ESP_HOSTED_RAW_TP_HOST_TO_ESP_PKT_LEN
|
|
depends on ESP_HOSTED_RAW_THROUGHPUT_TRANSPORT
|
|
int "RawTP: Host to ESP packet size"
|
|
range 1 1500
|
|
default 1460
|
|
|
|
config ESP_HOSTED_RAW_TP_REPORT_INTERVAL
|
|
depends on ESP_HOSTED_RAW_THROUGHPUT_TRANSPORT
|
|
int "RawTP: periodic duration to report stats accumulated"
|
|
default 5
|
|
|
|
config ESP_HOSTED_PKT_STATS
|
|
bool "Transport level packet stats"
|
|
default n
|
|
help
|
|
On comparing with slave packet stats helps to understand any packet loss at hosted
|
|
|
|
endmenu
|
|
|
|
menu "Data path options"
|
|
config ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE
|
|
bool "Report WiFi queue utilization to host"
|
|
default y
|
|
help
|
|
Proactively drop Host->slave Wi-Fi data when Slave Wi-Fi is under load
|
|
Slave Wi-Fi may drop ingress bursty or higher than capacity packets.
|
|
To have synchronous way of packet dropped for application,
|
|
Host will throttle incoming data if the slave datapath Rx load is high
|
|
|
|
config ESP_HOSTED_PRIV_WIFI_TX_SPI_HIGH_THRESHOLD
|
|
depends on ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE && ESP_HOSTED_SPI_HOST_INTERFACE
|
|
int "High threshold to report host to drop data when wifi highly loaded"
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range 0 100
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default 90
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help
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Host will throttle incoming data if the slave datapath Rx load goes beyond this threshold
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0 value will disable this function
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config ESP_HOSTED_PRIV_WIFI_TX_SDIO_HIGH_THRESHOLD
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depends on ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE && ESP_HOSTED_SDIO_HOST_INTERFACE
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int "High threshold to report host to drop data when wifi highly loaded"
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range 0 100
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default 80
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help
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Host will throttle incoming data if the slave datapath Rx load goes beyond this threshold
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0 value will disable this function
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config ESP_HOSTED_PRIV_WIFI_TX_SPI_HD_HIGH_THRESHOLD
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depends on ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE && ESP_HOSTED_SPI_HD_HOST_INTERFACE
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int "High threshold to report host to drop data when wifi highly loaded"
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|
range 0 100
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|
default 80
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help
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|
Host will throttle incoming data if the slave datapath Rx load goes beyond this threshold
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0 value will disable this function
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|
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config ESP_HOSTED_PRIV_WIFI_TX_UART_HIGH_THRESHOLD
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depends on ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE && ESP_HOSTED_UART_HOST_INTERFACE
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int "High threshold to report host to drop data when wifi highly loaded"
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|
range 0 100
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|
default 80
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|
help
|
|
Host will throttle incoming data if the slave datapath Rx load goes beyond this threshold
|
|
0 value will disable this function
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config ESP_HOSTED_TO_WIFI_DATA_THROTTLE_HIGH_THRESHOLD
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depends on ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE
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int
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default ESP_HOSTED_PRIV_WIFI_TX_SPI_HIGH_THRESHOLD if ESP_HOSTED_SPI_HOST_INTERFACE
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default ESP_HOSTED_PRIV_WIFI_TX_SDIO_HIGH_THRESHOLD if ESP_HOSTED_SDIO_HOST_INTERFACE
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default ESP_HOSTED_PRIV_WIFI_TX_SPI_HD_HIGH_THRESHOLD if ESP_HOSTED_SPI_HD_HOST_INTERFACE
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default ESP_HOSTED_PRIV_WIFI_TX_UART_HIGH_THRESHOLD if ESP_HOSTED_UART_HOST_INTERFACE
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config ESP_HOSTED_TO_WIFI_DATA_THROTTLE_LOW_THRESHOLD
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depends on ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE
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int "Low threshold to report host to stop dropping data"
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range 0 ESP_HOSTED_TO_WIFI_DATA_THROTTLE_HIGH_THRESHOLD
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default 60
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help
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|
Once the Wi-Fi is no more stressed, data throttling would be stopped, once slave Wi-Fi load
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is lower than this threshold
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endmenu
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config ESP_HOSTED_DECODE_WIFI_RESERVED_FIELD
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bool "Copy Wi-Fi configuration reserved field values"
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default n
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help
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ESP-IDF Wi-Fi structures contain reserved bitmask values.
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Enable this option if you want to copy these values between host and co-processor.
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It is usually safe to ignore these reserved values.
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endmenu
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