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update nimble library to version 1.40

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This commit is contained in:
technyon
2022-09-25 21:17:09 +02:00
parent 416feee527
commit f6bdf4ce9d
54 changed files with 3880 additions and 374 deletions
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4
lib/NimBLE-Arduino/src/nimble/nimble/drivers/nrf51/src/ble_phy.c
View File

@@ -1508,7 +1508,7 @@ ble_phy_resolv_list_disable(void)
void
ble_phy_rfclk_enable(void)
{
#if MYNEWT
#if MYNEWT || ARDUINO
nrf51_clock_hfxo_request();
#else
NRF_CLOCK->TASKS_HFCLKSTART = 1;
@@ -1518,7 +1518,7 @@ ble_phy_rfclk_enable(void)
void
ble_phy_rfclk_disable(void)
{
#if MYNEWT
#if MYNEWT || ARDUINO
nrf51_clock_hfxo_release();
#else
NRF_CLOCK->TASKS_HFCLKSTOP = 1;

6
lib/NimBLE-Arduino/src/nimble/nimble/drivers/nrf52/src/ble_phy.c
View File

@@ -16,7 +16,7 @@
* specific language governing permissions and limitations
* under the License.
*/
#if defined(ARDUINO_ARCH_NRF5) && defined(NRF52_SERIES)
#include <stdint.h>
@@ -2100,7 +2100,7 @@ void ble_phy_disable_dtm(void)
void
ble_phy_rfclk_enable(void)
{
#if MYNEWT
#if MYNEWT || ARDUINO
nrf52_clock_hfxo_request();
#else
NRF_CLOCK->TASKS_HFCLKSTART = 1;
@@ -2110,7 +2110,7 @@ ble_phy_rfclk_enable(void)
void
ble_phy_rfclk_disable(void)
{
#if MYNEWT
#if MYNEWT || ARDUINO
nrf52_clock_hfxo_release();
#else
NRF_CLOCK->TASKS_HFCLKSTOP = 1;

63
lib/NimBLE-Arduino/src/nimble/nimble/host/include/host/ble_gap.h
View File

@@ -1162,6 +1162,38 @@ int ble_gap_adv_rsp_set_fields(const struct ble_hs_adv_fields *rsp_fields);
int ble_hs_hci_util_set_data_len(uint16_t conn_handle, uint16_t tx_octets,
uint16_t tx_time);
/**
* Read host's suggested values for the controller's maximum transmitted number of payload octets
* and maximum packet transmission time (OGF = 0x08, OCF = 0x0024).
*
* @param out_sugg_max_tx_octets The Host's suggested value for the Controller's maximum transmitted
* number of payload octets in LL Data PDUs to be used for new
* connections. (Range 0x001B-0x00FB).
* @param out_sugg_max_tx_time The Host's suggested value for the Controller's maximum packet
* transmission time for packets containing LL Data PDUs to be used
* for new connections. (Range 0x0148-0x4290).
*
* @return 0 on success,
* other error code on failure.
*/
int ble_hs_hci_util_read_sugg_def_data_len(uint16_t *out_sugg_max_tx_octets,
uint16_t *out_sugg_max_tx_time);
/**
* Configure host's suggested maximum transmitted number of payload octets and maximum packet
* transmission time in controller (OGF = 0x08, OCF = 0x0024).
*
* @param sugg_max_tx_octets The Host's suggested value for the Controller's maximum transmitted
* number of payload octets in LL Data PDUs to be used for new
* connections. (Range 0x001B-0x00FB).
* @param sugg_max_tx_time The Host's suggested value for the Controller's maximum packet
* transmission time for packets containing LL Data PDUs to be used
* for new connections. (Range 0x0148-0x4290).
*
* @return 0 on success,
* other error code on failure.
*/
int ble_hs_hci_util_write_sugg_def_data_len(uint16_t sugg_max_tx_octets, uint16_t sugg_max_tx_time);
#if MYNEWT_VAL(BLE_EXT_ADV)
/** @brief Extended advertising parameters */
struct ble_gap_ext_adv_params {
@@ -1843,6 +1875,37 @@ int ble_gap_update_params(uint16_t conn_handle,
*/
int ble_gap_set_data_len(uint16_t conn_handle, uint16_t tx_octets, uint16_t tx_time);
/**
* Read LE Suggested Default Data Length in controller (OGF = 0x08, OCF = 0x0024).
*
* @param out_sugg_max_tx_octets The Host's suggested value for the Controller's maximum transmitted
* number of payload octets in LL Data PDUs to be used for new
* connections. (Range 0x001B-0x00FB).
* @param out_sugg_max_tx_time The Host's suggested value for the Controller's maximum packet
* transmission time for packets containing LL Data PDUs to be used
* for new connections. (Range 0x0148-0x4290).
*
* @return 0 on success,
* other error code on failure.
*/
int ble_gap_read_sugg_def_data_len(uint16_t *out_sugg_max_tx_octets,
uint16_t *out_sugg_max_tx_time);
/**
* Configure LE Suggested Default Data Length in controller (OGF = 0x08, OCF = 0x0024).
*
* @param sugg_max_tx_octets The Host's suggested value for the Controller's maximum transmitted
* number of payload octets in LL Data PDUs to be used for new
* connections. (Range 0x001B-0x00FB).
* @param sugg_max_tx_time The Host's suggested value for the Controller's maximum packet
* transmission time for packets containing LL Data PDUs to be used
* for new connections. (Range 0x0148-0x4290).
*
* @return 0 on success,
* other error code on failure.
*/
int ble_gap_write_sugg_def_data_len(uint16_t sugg_max_tx_octets, uint16_t sugg_max_tx_time);
/**
* Initiates the GAP security procedure.
*

2
lib/NimBLE-Arduino/src/nimble/nimble/host/mesh/src/net.c
View File

@@ -796,7 +796,7 @@ void bt_mesh_net_recv(struct os_mbuf *data, int8_t rssi,
* it again in the future.
*/
if (bt_mesh_trans_recv(buf, &rx) == -EAGAIN) {
BT_WARN("Removing rejected message from NetworkMessage Cache");
BT_WARN("Removing rejected message from Network Message Cache");
msg_cache[rx.msg_cache_idx].src = BT_MESH_ADDR_UNASSIGNED;
/* Rewind the next index now that we're not using this entry */
msg_cache_next = rx.msg_cache_idx;

10
lib/NimBLE-Arduino/src/nimble/nimble/host/src/ble_gap.c
View File

@@ -5860,6 +5860,16 @@ int ble_gap_set_data_len(uint16_t conn_handle, uint16_t tx_octets, uint16_t tx_t
return ble_hs_hci_util_set_data_len(conn_handle, tx_octets, tx_time);
}
int ble_gap_read_sugg_def_data_len(uint16_t *out_sugg_max_tx_octets, uint16_t *out_sugg_max_tx_time)
{
return ble_hs_hci_util_read_sugg_def_data_len(out_sugg_max_tx_octets, out_sugg_max_tx_time);
}
int ble_gap_write_sugg_def_data_len(uint16_t sugg_max_tx_octets, uint16_t sugg_max_tx_time)
{
return ble_hs_hci_util_write_sugg_def_data_len(sugg_max_tx_octets, sugg_max_tx_time);
}
/*****************************************************************************
* $security *
*****************************************************************************/

54
lib/NimBLE-Arduino/src/nimble/nimble/host/src/ble_hs_hci_util.c
View File

@@ -157,6 +157,60 @@ ble_hs_hci_util_set_data_len(uint16_t conn_handle, uint16_t tx_octets,
return 0;
}
int
ble_hs_hci_util_read_sugg_def_data_len(uint16_t *out_sugg_max_tx_octets,
uint16_t *out_sugg_max_tx_time)
{
struct ble_hci_le_rd_sugg_def_data_len_rp rsp;
int rc;
rc = ble_hs_hci_cmd_tx(BLE_HCI_OP(BLE_HCI_OGF_LE,
BLE_HCI_OCF_LE_RD_SUGG_DEF_DATA_LEN),
NULL, 0, &rsp, sizeof(rsp));
if (rc != 0) {
return rc;
}
*out_sugg_max_tx_octets = le16toh(rsp.max_tx_octets);
*out_sugg_max_tx_time = le16toh(rsp.max_tx_time);
if (*out_sugg_max_tx_octets < BLE_HCI_SUGG_DEF_DATALEN_TX_OCTETS_MIN ||
*out_sugg_max_tx_octets > BLE_HCI_SUGG_DEF_DATALEN_TX_OCTETS_MAX) {
BLE_HS_LOG(WARN, "received suggested maximum tx octets is out of range\n");
}
if (*out_sugg_max_tx_time < BLE_HCI_SUGG_DEF_DATALEN_TX_TIME_MIN ||
*out_sugg_max_tx_time > BLE_HCI_SUGG_DEF_DATALEN_TX_TIME_MAX) {
BLE_HS_LOG(WARN, "received suggested maximum tx time is out of range\n");
}
return 0;
}
int
ble_hs_hci_util_write_sugg_def_data_len(uint16_t sugg_max_tx_octets,
uint16_t sugg_max_tx_time)
{
struct ble_hci_le_wr_sugg_def_data_len_cp cmd;
if (sugg_max_tx_octets < BLE_HCI_SUGG_DEF_DATALEN_TX_OCTETS_MIN ||
sugg_max_tx_octets > BLE_HCI_SUGG_DEF_DATALEN_TX_OCTETS_MAX) {
return BLE_HS_EINVAL;
}
if (sugg_max_tx_time < BLE_HCI_SUGG_DEF_DATALEN_TX_TIME_MIN ||
sugg_max_tx_time > BLE_HCI_SUGG_DEF_DATALEN_TX_TIME_MAX) {
return BLE_HS_EINVAL;
}
cmd.max_tx_octets = htole16(sugg_max_tx_octets);
cmd.max_tx_time = htole16(sugg_max_tx_time);
return ble_hs_hci_cmd_tx(BLE_HCI_OP(BLE_HCI_OGF_LE,
BLE_HCI_OCF_LE_WR_SUGG_DEF_DATA_LEN),
&cmd, sizeof(cmd), NULL, 0);
}
int
ble_hs_hci_util_data_hdr_strip(struct os_mbuf *om,
struct hci_data_hdr *out_hdr)

5
lib/NimBLE-Arduino/src/nimble/nimble/host/src/ble_hs_periodic_sync.c
View File

@@ -43,7 +43,6 @@ ble_hs_periodic_sync_alloc(void)
memset(psync, 0, sizeof(*psync));
}
ble_npl_event_init(&psync->lost_ev, ble_gap_npl_sync_lost, psync);
return psync;
}
@@ -56,7 +55,9 @@ ble_hs_periodic_sync_free(struct ble_hs_periodic_sync *psync)
return;
}
ble_npl_event_deinit(&psync->lost_ev);
if((psync->lost_ev).event != NULL)
ble_npl_event_deinit(&psync->lost_ev);
#if MYNEWT_VAL(BLE_HS_DEBUG)
memset(psync, 0xff, sizeof *psync);
#endif

1
lib/NimBLE-Arduino/src/nimble/nimble/host/src/ble_hs_resolv.c
View File

@@ -97,6 +97,7 @@ ble_rpa_remove_peer_dev_rec(struct ble_hs_dev_records *p_dev_rec)
if ((i != ble_store_num_peer_dev_rec) && (ble_store_num_peer_dev_rec != 0)) {
memmove(&peer_dev_rec[i], &peer_dev_rec[i + 1],
(ble_store_num_peer_dev_rec - i) * sizeof(struct ble_hs_dev_records ));
memset(&peer_dev_rec[ble_store_num_peer_dev_rec], 0, sizeof(struct ble_hs_dev_records));
}
BLE_HS_LOG(DEBUG, " RPA: removed device at index = %d, no. of peer records"

9
lib/NimBLE-Arduino/src/nimble/nimble/host/src/ble_sm_alg.c
View File

@@ -643,6 +643,10 @@ mbedtls_gen_keypair(uint8_t *public_key, uint8_t *private_key)
mbedtls_entropy_init(&entropy);
mbedtls_ctr_drbg_init(&ctr_drbg);
/* Free the previously allocate keypair */
mbedtls_ecp_keypair_free(&keypair);
mbedtls_ecp_keypair_init(&keypair);
if (( rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy,
@@ -679,6 +683,11 @@ exit:
return 0;
}
void mbedtls_free_keypair(void)
{
mbedtls_ecp_keypair_free(&keypair);
}
#endif
/**

2
lib/NimBLE-Arduino/src/nimble/nimble/host/util/src/addr.c
View File

@@ -45,7 +45,7 @@ ble_hs_util_load_rand_addr(ble_addr_t *addr)
#if SOC_ESP_NIMBLE_CONTROLLER
int rc;
rc = esp_ble_hw_get_static_addr(addr);
rc = esp_ble_hw_get_static_addr((esp_ble_addr_t *)addr);
if (rc == 0) {
return 0;
}

2
lib/NimBLE-Arduino/src/nimble/nimble/include/nimble/ble_hci_trans.h
View File

@@ -66,7 +66,7 @@ struct os_mbuf;
typedef int ble_hci_trans_rx_cmd_fn(uint8_t *cmd, void *arg);
typedef int ble_hci_trans_rx_acl_fn(struct os_mbuf *om, void *arg);
#if CONFIG_IDF_TARGET_ESP32H2
#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
struct ble_hci_trans_funcs_t {
int(*_ble_hci_trans_hs_acl_tx)(struct os_mbuf *om);
int(*_ble_hci_trans_hs_cmd_tx)(uint8_t *cmd);

6
lib/NimBLE-Arduino/src/nimble/nimble/include/nimble/hci_common.h
View File

@@ -1215,6 +1215,12 @@ struct ble_hci_vs_rd_static_addr_rp {
#define BLE_HCI_SET_DATALEN_TX_TIME_MIN (0x0148)
#define BLE_HCI_SET_DATALEN_TX_TIME_MAX (0x4290)
/* --- LE read/write suggested default data length (OCF 0x0023 and 0x0024) */
#define BLE_HCI_SUGG_DEF_DATALEN_TX_OCTETS_MIN (0x001b)
#define BLE_HCI_SUGG_DEF_DATALEN_TX_OCTETS_MAX (0x00fb)
#define BLE_HCI_SUGG_DEF_DATALEN_TX_TIME_MIN (0x0148)
#define BLE_HCI_SUGG_DEF_DATALEN_TX_TIME_MAX (0x4290)
/* --- LE read maximum default PHY (OCF 0x0030) */
#define BLE_HCI_LE_PHY_1M (1)
#define BLE_HCI_LE_PHY_2M (2)

21
lib/NimBLE-Arduino/src/nimble/porting/nimble/include/nimble/nimble_port.h
View File

@@ -23,6 +23,7 @@
#include "nimble/nimble/include/nimble/nimble_npl.h"
#ifdef ESP_PLATFORM
#include "esp_err.h"
#include "nimconfig.h"
#define NIMBLE_CORE (CONFIG_BT_NIMBLE_PINNED_TO_CORE < portNUM_PROCESSORS ? CONFIG_BT_NIMBLE_PINNED_TO_CORE : tskNO_AFFINITY)
#define NIMBLE_HS_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE
@@ -31,8 +32,8 @@
#define NIMBLE_HS_STACK_SIZE (CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE / 4)
#endif
#if (CONFIG_IDF_TARGET_ESP32H2)
#define NIMBLE_LL_STACK_SIZE CONFIG_BT_NIMBLE_CONTROLLER_TASK_STACK_SIZE
#if (CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2)
#define NIMBLE_LL_STACK_SIZE CONFIG_BT_LE_CONTROLLER_TASK_STACK_SIZE
#endif
#ifdef __cplusplus
@@ -45,6 +46,22 @@ void nimble_port_deinit(void);
void nimble_port_run(void);
int nimble_port_stop(void);
#ifdef ESP_PLATFORM
/**
* @brief esp_nimble_init - Initialize the NimBLE host stack
*
* @return esp_err_t
*/
esp_err_t esp_nimble_init(void);
/**
* @brief esp_nimble_deinit - Deinitialize the NimBLE host stack
*
* @return esp_err_t
*/
esp_err_t esp_nimble_deinit(void);
#endif // ESP_PLATFORM
struct ble_npl_eventq *nimble_port_get_dflt_eventq(void);
#if NIMBLE_CFG_CONTROLLER

7
lib/NimBLE-Arduino/src/nimble/porting/nimble/include/syscfg/syscfg.h
View File

@@ -6,9 +6,12 @@
#define H_SYSCFG_
#ifdef ESP_PLATFORM
#include "nimble/esp_port/port/include/esp_nimble_cfg.h"
# include "nimble/esp_port/port/include/esp_nimble_cfg.h"
#else
#include "ext_nimble_config.h"
# include "ext_nimble_config.h"
# ifndef CONFIG_BT_NIMBLE_ENABLED
# define CONFIG_BT_NIMBLE_ENABLED 1
# endif
#endif
#if 0

388
lib/NimBLE-Arduino/src/nimble/porting/nimble/src/hal_uart.c Normal file
View File

@@ -0,0 +1,388 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
#include "freertos/FreeRTOS.h"
#include "os/os.h"
#include "hal/hal_uart.h"
#include "soc/soc.h"
#include "soc/system_reg.h"
#include "driver/gpio.h"
#include "esp_intr_alloc.h"
#include "riscv/interrupt.h"
#include "hal/uart_ll.h"
#include "freertos/semphr.h"
#include "rom/ets_sys.h"
#include "driver/uart.h"
#include "driver/periph_ctrl.h"
struct hal_uart {
uint8_t u_open:1;
uint8_t u_rx_stall:1;
uint8_t u_tx_started:1;
uint8_t u_tx_buf;
hal_uart_rx_char u_rx_func;
hal_uart_tx_char u_tx_func;
hal_uart_tx_done u_tx_done;
SemaphoreHandle_t u_rx_sem;
void *u_func_arg;
};
static struct hal_uart uart;
#define UART_FIFO_LEN (128)
uint8_t rxbuffer[256];
static uint16_t rd_ptr = 0;
static uint16_t wr_ptr = 0;
#define BUFFER_MASK (0xff)
static TaskHandle_t hci_uart_task_h;
void uart_init(uint32_t baud);
void uart0_init(uint32_t baud);
void uart0_tout_isr(void);
void uart_tout_isr(void);
void
hal_uart_blocking_tx(int port, uint8_t data){
}
int hal_uart_init(int uart_no, void *cfg)
{
// Uart_Init(uart_no, UART_CLK_FREQ_ROM);
return 0;
}
void hal_uart_start_rx(int uart)
{
ets_printf("rx support???\n");
}
int hal_uart_init_cbs(int uart_no, hal_uart_tx_char tx_func,
hal_uart_tx_done tx_done, hal_uart_rx_char rx_func, void *arg)
{
struct hal_uart *u;
u = &uart;
if (u->u_open) {
return -1;
}
u->u_rx_func = rx_func;
u->u_tx_func = tx_func;
u->u_tx_done = tx_done;
u->u_func_arg = arg;
return 0;
}
int hal_uart_config(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits,
enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
{
struct hal_uart *u;
u = &uart;
if (u->u_open) {
return -1;
}
if (uart_no) {
uart_init(speed);
} else {
uart0_init(speed);
}
u->u_open = 1;
return 0;
}
static int
IRAM_ATTR_64MCPU hal_uart_tx_fill_buf(struct hal_uart *u, int uart_no)
{
int data;
int i;
uart_dev_t *hw = &UART1;
if(!uart_no){
hw = &UART0;
}
i = 0;
while(hw->status.txfifo_cnt < UART_FIFO_LEN){
data = u->u_tx_func(u->u_func_arg);
if (data >= 0) {
hw->ahb_fifo.rw_byte = data;
i++;
}else{
break;
}
}
return i;
}
void hal_uart_start_tx(int uart_no)
{
struct hal_uart *u;
os_sr_t sr;
uart_dev_t *hw = &UART1;
if(!uart_no){
hw = &UART0;
}
u = &uart;
OS_ENTER_CRITICAL(sr);
if (u->u_tx_started == 0) {
u->u_tx_started = 1;
hw->int_ena.tx_done = 1;
hal_uart_tx_fill_buf(u,uart_no);
}
OS_EXIT_CRITICAL(sr);
}
int hal_uart0_close(int uart_no)
{
struct hal_uart *u;
u = &uart;
u->u_open = 0;
REG_CLR_BIT(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART_CLK_EN);
REG_SET_BIT(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST);
return 0;
}
int hal_uart_close(int uart_no)
{
struct hal_uart *u;
u = &uart;
u->u_open = 0;
REG_CLR_BIT(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART1_CLK_EN);
REG_SET_BIT(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST);
return 0;
}
IRAM_ATTR_64MCPU void uart0_tout_isr(void)
{
struct hal_uart *u;
int rc;
uint32_t ch;
uart_dev_t *hw = &UART0;
u = &uart;
uint32_t uart_int_st = hw->int_st.val;
//clear
hw->int_clr.val = uart_int_st;
if (uart_int_st&UART_TX_DONE_INT_ST_M) {
rc = hal_uart_tx_fill_buf(u,0);
if (rc == 0) {
if (u->u_tx_done) {
u->u_tx_done(u->u_func_arg);
}
u->u_tx_started = 0;
hw->int_ena.tx_done = 0;
}
}
while (hw->status.rxfifo_cnt) {
int rd_len = hw->status.rxfifo_cnt;
for (int i = 0; i < rd_len; i++) {
ch = hw->ahb_fifo.rw_byte;
rc = u->u_rx_func(u->u_func_arg, ch);
if (rc < 0) {
u->u_rx_stall = 1;
}
}
}
}
IRAM_ATTR_64MCPU void uart_tout_isr(void)
{
struct hal_uart *u;
int rc;
bool rx_update = false;
uart_dev_t *hw = &UART1;
u = &uart;
uint32_t uart_int_st = hw->int_st.val;
//clear
hw->int_clr.val = uart_int_st;
if (uart_int_st&UART_TX_DONE_INT_ST_M) {
rc = hal_uart_tx_fill_buf(u,1);
if (rc == 0) {
if (u->u_tx_done) {
u->u_tx_done(u->u_func_arg);
}
u->u_tx_started = 0;
hw->int_ena.tx_done = 0;
}
}
while (hw->status.rxfifo_cnt) {
rxbuffer[(wr_ptr++)&BUFFER_MASK] = hw->ahb_fifo.rw_byte;
rx_update = true;
}
if (rx_update) {
xSemaphoreGiveFromISR(u->u_rx_sem, 0);
}
}
void
IRAM_ATTR uart_rx_task(void *arg){
int rc;
struct hal_uart *u;
u = &uart;
while (1) {
xSemaphoreTake(u->u_rx_sem, portMAX_DELAY);
while (rd_ptr != wr_ptr){
rc = u->u_rx_func(u->u_func_arg, rxbuffer[(rd_ptr++)&BUFFER_MASK]);
if (rc < 0) {
u->u_rx_stall = 1;
}
}
}
}
void uart0_init(uint32_t baud)
{
REG_SET_BIT(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST);
REG_CLR_BIT(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST);
REG_CLR_BIT(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART_CLK_EN_M);
REG_SET_BIT(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART_CLK_EN_M);
const int sclk_div = 1;
uint32_t sclk_freq = XTAL_CLK_FREQ;
uint32_t clk_div = ((sclk_freq) << 4) / baud;
uart_dev_t *hw = &UART0;
hw->clk_conf.sclk_en = 0;
hw->clk_conf.rx_sclk_en = 0;
hw->clk_conf.tx_sclk_en = 0;
hw->clk_conf.sclk_en = 1;
hw->clk_conf.rx_sclk_en = 1;
hw->clk_conf.tx_sclk_en = 1;
hw->clk_div.div_int = clk_div >> 4;
hw->clk_div.div_frag = clk_div & 0xf;
hw->clk_conf.sclk_div_num = sclk_div - 1;//7;//255;
hw->conf0.parity_en = 0;
hw->conf0.irda_en = 0;
hw->rs485_conf.en = 0;
hw->rs485_conf.tx_rx_en = 0;
hw->rs485_conf.rx_busy_tx_en = 0;
hw->conf0.bit_num = 3;
hw->conf0.stop_bit_num = 1;
hw->conf1.rxfifo_full_thrhd = 80;
hw->mem_conf.rx_tout_thrhd = 20;
hw->conf1.rx_tout_en = 1;
hw->conf1.rx_flow_en = 0;
hw->conf0.tx_flow_en = 0;
hw->conf0.rxfifo_rst = 1;
hw->conf0.rxfifo_rst = 0;
hw->conf0.txfifo_rst = 1;
hw->conf0.txfifo_rst = 0;
hw->int_ena.rxfifo_full = 1;
//enable rx fifo timeout interrupt
hw->int_ena.rxfifo_tout = 1;
uint8_t tx_pin = 21, rx_pin = 20, ISR_ID = ETS_UART0_INUM;
ets_isr_mask((1<<ISR_ID)); //ETS_INTR_DISABLE
intr_handler_set(ISR_ID, (intr_handler_t)&uart0_tout_isr, NULL);
intr_matrix_route(ETS_UART0_INTR_SOURCE, ISR_ID);
esprv_intc_int_enable(BIT(ISR_ID));
esprv_intc_int_set_type(BIT(ISR_ID), INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ISR_ID, 1);
esp_intr_reserve(ISR_ID, xPortGetCoreID());
ESP_ERROR_CHECK(uart_set_pin(0, tx_pin, rx_pin, -1, -1));
}
void uart_init(uint32_t baud)
{
periph_module_enable(PERIPH_UART1_MODULE);
REG_SET_BIT(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST);
REG_CLR_BIT(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST);
REG_CLR_BIT(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART1_CLK_EN_M);
REG_SET_BIT(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART1_CLK_EN_M);
const int sclk_div = 1;
uint32_t sclk_freq = XTAL_CLK_FREQ;
uint32_t clk_div = ((sclk_freq) << 4) / baud;
struct hal_uart *u = &uart;
uart_dev_t *hw = &UART1;
hw->clk_conf.sclk_en = 0;
hw->clk_conf.rx_sclk_en = 0;
hw->clk_conf.tx_sclk_en = 0;
hw->clk_conf.sclk_en = 1;
hw->clk_conf.rx_sclk_en = 1;
hw->clk_conf.tx_sclk_en = 1;
hw->clk_div.div_int = clk_div >> 4;
hw->clk_div.div_frag = clk_div & 0xf;
hw->clk_conf.sclk_div_num = sclk_div - 1;//7;//255;
hw->conf0.parity_en = 0;
hw->conf0.irda_en = 0;
hw->rs485_conf.en = 0;
hw->rs485_conf.tx_rx_en = 0;
hw->rs485_conf.rx_busy_tx_en = 0;
hw->conf0.bit_num = 3;
hw->conf0.stop_bit_num = 1;
//set full threshold to (2/3)*FIFO_LEN
hw->conf1.rxfifo_full_thrhd = 80;
hw->mem_conf.rx_tout_thrhd = 20;
hw->conf1.rx_tout_en = 1;
hw->conf0.rxfifo_rst = 1;
hw->conf0.rxfifo_rst = 0;
hw->conf0.txfifo_rst = 1;
hw->conf0.txfifo_rst = 0;
hw->int_ena.rxfifo_full = 1;
//enable rx fifo timeout interrupt
hw->int_ena.rxfifo_tout = 1;
u->u_rx_sem = xSemaphoreCreateBinary();
uint8_t TX_IO = CONFIG_BT_LE_HCI_UART_TX_PIN, RX_IO = CONFIG_BT_LE_HCI_UART_RX_PIN, ISR_ID = ETS_UART1_INUM;
printf("set nimble port tx:%d, rx:%d.\n", TX_IO, RX_IO);
printf("set baud:%d.\n", baud);
intr_handler_set(ISR_ID, (intr_handler_t)&uart_tout_isr, NULL);
intr_matrix_route(ETS_UART1_INTR_SOURCE, ISR_ID);
esprv_intc_int_enable(BIT(ISR_ID));
esprv_intc_int_set_type(BIT(ISR_ID), INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ISR_ID, 1);
// TODO ESP32-C3 IDF-2126, maybe can use interrupt allocation API for all of the above? unsure...
esp_intr_reserve(ISR_ID, xPortGetCoreID());
ESP_ERROR_CHECK(uart_set_pin(1, TX_IO, RX_IO, -1, -1));
//Enable hw flow control of UART1 for BQB test, which if not enabled, the tester takes quite long time to send a byte to DUT
// uart_ll_set_hw_flow_ctrl(hw, UART_HW_FLOWCTRL_CTS_RTS, 110);
xTaskCreate(uart_rx_task, "uart_rx", CONFIG_BT_LE_HCI_UART_TASK_STACK_SIZE,
NULL, 1, &hci_uart_task_h);
}
#endif // CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2

227
lib/NimBLE-Arduino/src/nimble/porting/nimble/src/nimble_port.c
View File

@@ -20,7 +20,11 @@
#include <stddef.h>
#include "../include/os/os.h"
#include "../include/sysinit/sysinit.h"
#if CONFIG_BT_NIMBLE_ENABLED
#include "nimble/nimble/host/include/host/ble_hs.h"
#endif //CONFIG_BT_NIMBLE_ENABLED
#include "../include/nimble/nimble_port.h"
#include "../../npl/freertos/include/nimble/nimble_port_freertos.h"
#if NIMBLE_CFG_CONTROLLER
@@ -43,91 +47,31 @@
#endif
#endif
#ifdef CONFIG_BT_NIMBLE_CONTROL_USE_UART_HCI
#include "transport/uart/ble_hci_uart.h"
#else
#include "nimble/nimble/transport/ram/include/transport/ram/ble_hci_ram.h"
#endif
#include "nimble/nimble/include/nimble/ble_hci_trans.h"
#ifdef ESP_PLATFORM
#include "esp_intr_alloc.h"
#include "esp_bt.h"
#include "nimble/esp_port/esp-hci/include/esp_nimble_hci.h"
#endif
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
extern void ble_hs_deinit(void);
#define NIMBLE_PORT_LOG_TAG "BLE_INIT"
extern void os_msys_init(void);
static struct ble_npl_eventq g_eventq_dflt;
#if CONFIG_BT_NIMBLE_ENABLED
extern void ble_hs_deinit(void);
static struct ble_hs_stop_listener stop_listener;
#endif //CONFIG_BT_NIMBLE_ENABLED
static struct ble_npl_eventq g_eventq_dflt;
static struct ble_npl_sem ble_hs_stop_sem;
static struct ble_npl_event ble_hs_ev_stop;
void
nimble_port_init(void)
{
#if SOC_ESP_NIMBLE_CONTROLLER
struct esp_bt_controller_config_t config_opts = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
if(esp_bt_controller_init(&config_opts) != 0) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "controller init failed\n");
return;
}
/* Initialize the host */
ble_hs_init();
#else //SOC_ESP_NIMBLE_CONTROLLER
#if CONFIG_NIMBLE_STACK_USE_MEM_POOLS
/* Initialize the function pointers for OS porting */
npl_freertos_funcs_init();
npl_freertos_mempool_init();
#endif
/* Initialize default event queue */
ble_npl_eventq_init(&g_eventq_dflt);
#if NIMBLE_CFG_CONTROLLER
void ble_hci_ram_init(void);
#endif
os_msys_init();
ble_hs_init();
#endif
#ifndef ESP_PLATFORM
# if NIMBLE_CFG_CONTROLLER
ble_hci_ram_init();
hal_timer_init(5, NULL);
os_cputime_init(32768);
ble_ll_init();
# endif
#endif
}
void
nimble_port_deinit(void)
{
#if SOC_ESP_NIMBLE_CONTROLLER
ble_hs_deinit();
esp_bt_controller_deinit();
/* Delete the host task */
nimble_port_freertos_deinit();
#else
ble_npl_eventq_deinit(&g_eventq_dflt);
ble_hs_deinit();
#endif
}
/**
* Called when the host stop procedure has completed.
*/
@@ -143,12 +87,150 @@ nimble_port_stop_cb(struct ble_npl_event *ev)
ble_npl_sem_release(&ble_hs_stop_sem);
}
#ifdef ESP_PLATFORM
/**
* @brief esp_nimble_init - Initialize the NimBLE host stack
*
* @return esp_err_t
*/
esp_err_t esp_nimble_init(void)
{
#if !SOC_ESP_NIMBLE_CONTROLLER
#if CONFIG_NIMBLE_STACK_USE_MEM_POOLS
/* Initialize the function pointers for OS porting */
npl_freertos_funcs_init();
npl_freertos_mempool_init();
#endif
#if false //need delete esp_nimble_hci_and_controller_init then can be use
if(esp_nimble_hci_init() != ESP_OK) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "hci inits failed\n");
return ESP_FAIL;
}
printf("esp_nimble_hci_init\n");
#endif
/* Initialize default event queue */
ble_npl_eventq_init(&g_eventq_dflt);
os_msys_init();
#endif
/* Initialize the host */
ble_hs_init();
return ESP_OK;
}
/**
* @brief esp_nimble_deinit - Deinitialize the NimBLE host stack
*
* @return esp_err_t
*/
esp_err_t esp_nimble_deinit(void)
{
#if false && !SOC_ESP_NIMBLE_CONTROLLER //need delete esp_nimble_hci_and_controller_init then can be use
if(esp_nimble_hci_deinit() != ESP_OK) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "hci deinit failed\n");
return ESP_FAIL;
}
#endif
#if !(SOC_ESP_NIMBLE_CONTROLLER && CONFIG_BT_CONTROLLER_ENABLED)
ble_npl_eventq_deinit(&g_eventq_dflt);
#endif
ble_hs_deinit();
return ESP_OK;
}
#endif
void
nimble_port_init(void)
{
#ifdef ESP_PLATFORM
#if SOC_ESP_NIMBLE_CONTROLLER && CONFIG_BT_CONTROLLER_ENABLED
esp_bt_controller_config_t config_opts = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
if(esp_bt_controller_init(&config_opts) != ESP_OK) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "controller init failed\n");
return;
}
if(esp_bt_controller_enable(ESP_BT_MODE_BLE) != ESP_OK) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "controller enable failed\n");
return;
}
#endif
if(esp_nimble_init() != 0) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "nimble host init failed\n");
return;
}
#else
#if CONFIG_NIMBLE_STACK_USE_MEM_POOLS
/* Initialize the function pointers for OS porting */
npl_freertos_funcs_init();
npl_freertos_mempool_init();
#endif
/* Initialize default event queue */
ble_npl_eventq_init(&g_eventq_dflt);
os_msys_init();
ble_hs_init();
#if NIMBLE_CFG_CONTROLLER
ble_hci_ram_init();
hal_timer_init(5, NULL);
os_cputime_init(32768);
ble_ll_init();
#endif
#endif // ESP_PLATFORM
}
void
nimble_port_deinit(void)
{
#ifdef ESP_PLATFORM
if(esp_nimble_deinit() != 0) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "nimble host deinit failed\n");
return;
}
#if CONFIG_BT_CONTROLLER_ENABLED
if(esp_bt_controller_disable() != ESP_OK) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "controller disable failed\n");
return;
}
if(esp_bt_controller_deinit() != ESP_OK) {
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "controller deinit failed\n");
return;
}
#endif
#else
ble_npl_eventq_deinit(&g_eventq_dflt);
ble_hs_deinit();
#endif // ESP_PLATFORM
}
int
nimble_port_stop(void)
{
int rc;
#ifdef ESP_PLATFORM
esp_err_t err = ESP_OK;
ble_npl_sem_init(&ble_hs_stop_sem, 0);
/* Initiate a host stop procedure. */
err = ble_hs_stop(&stop_listener, ble_hs_stop_cb,
NULL);
if (err != 0) {
ble_npl_sem_deinit(&ble_hs_stop_sem);
return err;
}
#else
int rc = 0;
ble_npl_sem_init(&ble_hs_stop_sem, 0);
/* Initiate a host stop procedure. */
rc = ble_hs_stop(&stop_listener, ble_hs_stop_cb,
NULL);
@@ -156,12 +238,13 @@ nimble_port_stop(void)
ble_npl_sem_deinit(&ble_hs_stop_sem);
return rc;
}
#endif // ESP_PLATFORM
/* Wait till the host stop procedure is complete */
ble_npl_sem_pend(&ble_hs_stop_sem, BLE_NPL_TIME_FOREVER);
ble_npl_event_init(&ble_hs_ev_stop, nimble_port_stop_cb,
NULL);
NULL);
ble_npl_eventq_put(&g_eventq_dflt, &ble_hs_ev_stop);
/* Wait till the event is serviced */
@@ -169,7 +252,11 @@ nimble_port_stop(void)
ble_npl_sem_deinit(&ble_hs_stop_sem);
#ifdef ESP_PLATFORM
return ESP_OK;
#else
return rc;
#endif
}
void

42
lib/NimBLE-Arduino/src/nimble/porting/nimble/src/os_msys_init.c
View File

@@ -30,11 +30,25 @@
static STAILQ_HEAD(, os_mbuf_pool) g_msys_pool_list =
STAILQ_HEAD_INITIALIZER(g_msys_pool_list);
#if MYNEWT_VAL(MSYS_1_BLOCK_COUNT) > 0
#if CONFIG_BT_NIMBLE_ENABLED
#define OS_MSYS_1_BLOCK_COUNT MYNEWT_VAL(MSYS_1_BLOCK_COUNT)
#define OS_MSYS_1_BLOCK_SIZE MYNEWT_VAL(MSYS_1_BLOCK_SIZE)
#define OS_MSYS_2_BLOCK_COUNT MYNEWT_VAL(MSYS_2_BLOCK_COUNT)
#define OS_MSYS_2_BLOCK_SIZE MYNEWT_VAL(MSYS_2_BLOCK_SIZE)
#else
#define OS_MSYS_1_BLOCK_COUNT CONFIG_BT_LE_MSYS_1_BLOCK_COUNT
#define OS_MSYS_1_BLOCK_SIZE CONFIG_BT_LE_MSYS_1_BLOCK_SIZE
#define OS_MSYS_2_BLOCK_COUNT CONFIG_BT_LE_MSYS_2_BLOCK_COUNT
#define OS_MSYS_2_BLOCK_SIZE CONFIG_BT_LE_MSYS_2_BLOCK_SIZE
#endif
#if OS_MSYS_1_BLOCK_COUNT > 0
#define SYSINIT_MSYS_1_MEMBLOCK_SIZE \
OS_ALIGN(MYNEWT_VAL(MSYS_1_BLOCK_SIZE), 4)
OS_ALIGN(OS_MSYS_1_BLOCK_SIZE, 4)
#define SYSINIT_MSYS_1_MEMPOOL_SIZE \
OS_MEMPOOL_SIZE(MYNEWT_VAL(MSYS_1_BLOCK_COUNT), \
OS_MEMPOOL_SIZE(OS_MSYS_1_BLOCK_COUNT, \
SYSINIT_MSYS_1_MEMBLOCK_SIZE)
#ifdef ESP_PLATFORM
static os_membuf_t *os_msys_init_1_data;
@@ -45,11 +59,11 @@ static struct os_mbuf_pool os_msys_init_1_mbuf_pool;
static struct os_mempool os_msys_init_1_mempool;
#endif
#if MYNEWT_VAL(MSYS_2_BLOCK_COUNT) > 0
#if OS_MSYS_2_BLOCK_COUNT > 0
#define SYSINIT_MSYS_2_MEMBLOCK_SIZE \
OS_ALIGN(MYNEWT_VAL(MSYS_2_BLOCK_SIZE), 4)
OS_ALIGN(OS_MSYS_2_BLOCK_SIZE, 4)
#define SYSINIT_MSYS_2_MEMPOOL_SIZE \
OS_MEMPOOL_SIZE(MYNEWT_VAL(MSYS_2_BLOCK_COUNT), \
OS_MEMPOOL_SIZE(OS_MSYS_2_BLOCK_COUNT, \
SYSINIT_MSYS_2_MEMBLOCK_SIZE)
#ifdef ESP_PLATFORM
static os_membuf_t *os_msys_init_2_data;
@@ -135,14 +149,14 @@ os_msys_init_once(void *data, struct os_mempool *mempool,
int
os_msys_buf_alloc(void)
{
#if MYNEWT_VAL(MSYS_1_BLOCK_COUNT) > 0
#if OS_MSYS_1_BLOCK_COUNT > 0
os_msys_init_1_data = (os_membuf_t *)nimble_platform_mem_calloc(1, (sizeof(os_membuf_t) * SYSINIT_MSYS_1_MEMPOOL_SIZE));
if (!os_msys_init_1_data) {
return ESP_FAIL;
}
#endif
#if MYNEWT_VAL(MSYS_2_BLOCK_COUNT) > 0
#if OS_MSYS_2_BLOCK_COUNT > 0
os_msys_init_2_data = (os_membuf_t *)nimble_platform_mem_calloc(1, (sizeof(os_membuf_t) * SYSINIT_MSYS_2_MEMPOOL_SIZE));
if (!os_msys_init_2_data) {
return ESP_FAIL;
@@ -155,12 +169,12 @@ os_msys_buf_alloc(void)
void
os_msys_buf_free(void)
{
#if MYNEWT_VAL(MSYS_1_BLOCK_COUNT) > 0
#if OS_MSYS_1_BLOCK_COUNT > 0
nimble_platform_mem_free(os_msys_init_1_data);
os_msys_init_1_data = NULL;
#endif
#if MYNEWT_VAL(MSYS_2_BLOCK_COUNT) > 0
#if OS_MSYS_2_BLOCK_COUNT > 0
nimble_platform_mem_free(os_msys_init_2_data);
os_msys_init_2_data = NULL;
#endif
@@ -176,20 +190,20 @@ void os_msys_init(void)
os_msys_reset();
#if MYNEWT_VAL(MSYS_1_BLOCK_COUNT) > 0
#if OS_MSYS_1_BLOCK_COUNT > 0
os_msys_init_once(os_msys_init_1_data,
&os_msys_init_1_mempool,
&os_msys_init_1_mbuf_pool,
MYNEWT_VAL(MSYS_1_BLOCK_COUNT),
OS_MSYS_1_BLOCK_COUNT,
SYSINIT_MSYS_1_MEMBLOCK_SIZE,
"msys_1");
#endif
#if MYNEWT_VAL(MSYS_2_BLOCK_COUNT) > 0
#if OS_MSYS_2_BLOCK_COUNT > 0
os_msys_init_once(os_msys_init_2_data,
&os_msys_init_2_mempool,
&os_msys_init_2_mbuf_pool,
MYNEWT_VAL(MSYS_2_BLOCK_COUNT),
OS_MSYS_2_BLOCK_COUNT,
SYSINIT_MSYS_2_MEMBLOCK_SIZE,
"msys_2");
#endif

25
lib/NimBLE-Arduino/src/nimble/porting/npl/freertos/include/nimble/nimble_port_freertos.h
View File

@@ -23,22 +23,45 @@
#include "nimble/nimble/include/nimble/nimble_npl.h"
#include "nimble/porting/nimble/include/syscfg/syscfg.h"
#ifdef ESP_PLATFORM
#include "esp_err.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef ESP_PLATFORM
/**
* @brief esp_nimble_enable - Initialize the NimBLE host task
*
* @param host_task
* @return esp_err_t
*/
esp_err_t esp_nimble_enable(void *host_task);
/**
* @brief esp_nimble_disable - Disable the NimBLE host task
*
* @return esp_err_t
*/
esp_err_t esp_nimble_disable(void);
#endif
void nimble_port_freertos_init(TaskFunction_t host_task_fn);
void nimble_port_freertos_deinit(void);
#if CONFIG_NIMBLE_STACK_USE_MEM_POOLS
void npl_freertos_funcs_init(void);
void npl_freertos_funcs_deinit(void);
int npl_freertos_mempool_init(void);
struct npl_funcs_t * npl_freertos_funcs_get(void);
#endif
#ifndef ESP_PLATFORM
UBaseType_t nimble_port_freertos_get_ll_hwm(void);
#endif
UBaseType_t nimble_port_freertos_get_hs_hwm(void);
#endif
#ifdef __cplusplus
}

63
lib/NimBLE-Arduino/src/nimble/porting/npl/freertos/src/nimble_port_freertos.c
View File

@@ -41,7 +41,51 @@ static StackType_t hs_xStack[ NIMBLE_HS_STACK_SIZE ];
static StaticTask_t hs_xTaskBuffer;
#endif
static TaskHandle_t host_task_h;
static TaskHandle_t host_task_h = NULL;
#ifdef ESP_PLATFORM
/**
* @brief esp_nimble_enable - Initialize the NimBLE host
*
* @param host_task
* @return esp_err_t
*/
esp_err_t esp_nimble_enable(void *host_task)
{
/*
* Create task where NimBLE host will run. It is not strictly necessary to
* have separate task for NimBLE host, but since something needs to handle
* default queue it is just easier to make separate task which does this.
*/
xTaskCreatePinnedToCore(host_task, "nimble_host", NIMBLE_HS_STACK_SIZE,
NULL, (configMAX_PRIORITIES - 4), &host_task_h, NIMBLE_CORE);
return ESP_OK;
}
/**
* @brief esp_nimble_disable - Disable the NimBLE host
*
* @return esp_err_t
*/
esp_err_t esp_nimble_disable(void)
{
if (host_task_h) {
vTaskDelete(host_task_h);
host_task_h = NULL;
}
return ESP_OK;
}
// Compatibility wrappers for new functions
void nimble_port_freertos_init(TaskFunction_t host_task_fn) {
esp_nimble_enable((void*)host_task_fn);
}
void nimble_port_freertos_deinit(void) {
esp_nimble_disable();
}
#else // ESP_PLATFORM
void
nimble_port_freertos_init(TaskFunction_t host_task_fn)
@@ -53,26 +97,16 @@ nimble_port_freertos_init(TaskFunction_t host_task_fn)
* provided by NimBLE and in case of FreeRTOS it does not need to be wrapped
* since it has compatible prototype.
*/
#ifdef ESP_PLATFORM
esp_bt_controller_enable(ESP_BT_MODE_BLE);
#else
ll_task_h = xTaskCreateStatic(nimble_port_ll_task_func, "ll", NIMBLE_LL_STACK_SIZE,
NULL, configMAX_PRIORITIES, ll_xStack, &ll_xTaskBuffer);
#endif
#endif
/*
* Create task where NimBLE host will run. It is not strictly necessary to
* have separate task for NimBLE host, but since something needs to handle
* default queue it is just easier to make separate task which does this.
*/
#ifdef ESP_PLATFORM
xTaskCreatePinnedToCore(host_task_fn, "ble", NIMBLE_HS_STACK_SIZE,
NULL, (configMAX_PRIORITIES - 4), &host_task_h, NIMBLE_CORE);
#else
host_task_h = xTaskCreateStatic(host_task_fn, "ble", NIMBLE_HS_STACK_SIZE,
NULL, (configMAX_PRIORITIES - 1), hs_xStack, &hs_xTaskBuffer);
#endif
}
void
@@ -81,12 +115,8 @@ nimble_port_freertos_deinit(void)
if (host_task_h) {
vTaskDelete(host_task_h);
}
#ifdef ESP_PLATFORM
esp_bt_controller_disable();
#endif
}
#ifndef ESP_PLATFORM
#if NIMBLE_CFG_CONTROLLER
UBaseType_t
nimble_port_freertos_get_ll_hwm(void)
@@ -94,10 +124,11 @@ nimble_port_freertos_get_ll_hwm(void)
return uxTaskGetStackHighWaterMark(ll_task_h);
}
#endif
#endif
UBaseType_t
nimble_port_freertos_get_hs_hwm(void)
{
return uxTaskGetStackHighWaterMark(host_task_h);
}
#endif //ESP_PLATFORM

63
lib/NimBLE-Arduino/src/nimble/porting/npl/freertos/src/npl_os_freertos.c
View File

@@ -60,14 +60,28 @@ static const char *TAG = "Timer";
#define OS_MEM_ALLOC (1)
#if CONFIG_BT_NIMBLE_ENABLED
#define BT_LE_HCI_EVT_HI_BUF_COUNT MYNEWT_VAL(BLE_HCI_EVT_HI_BUF_COUNT)
#define BT_LE_HCI_EVT_LO_BUF_COUNT MYNEWT_VAL(BLE_HCI_EVT_LO_BUF_COUNT)
#define BT_LE_MAX_EXT_ADV_INSTANCES MYNEWT_VAL(BLE_MULTI_ADV_INSTANCES)
#define BT_LE_MAX_CONNECTIONS MYNEWT_VAL(BLE_MAX_CONNECTIONS)
#else
#include "esp_bt.h"
#define BT_LE_HCI_EVT_HI_BUF_COUNT DEFAULT_BT_LE_HCI_EVT_HI_BUF_COUNT
#define BT_LE_HCI_EVT_LO_BUF_COUNT DEFAULT_BT_LE_HCI_EVT_LO_BUF_COUNT
#define BT_LE_MAX_EXT_ADV_INSTANCES DEFAULT_BT_LE_MAX_EXT_ADV_INSTANCES
#define BT_LE_MAX_CONNECTIONS DEFAULT_BT_LE_MAX_CONNECTIONS
#endif
#define BLE_HS_HCI_EVT_COUNT \
(MYNEWT_VAL(BLE_HCI_EVT_HI_BUF_COUNT) + \
MYNEWT_VAL(BLE_HCI_EVT_LO_BUF_COUNT))
(BT_LE_HCI_EVT_HI_BUF_COUNT + \
BT_LE_HCI_EVT_LO_BUF_COUNT)
#define LL_NPL_BASE_EVENT_COUNT (11)
#define LL_SCAN_EXT_AUX_EVT_CNT (MYNEWT_VAL(BLE_LL_EXT_ADV_AUX_PTR_CNT))
#define HCI_LL_NPL_EVENT_COUNT (1)
#define ADV_LL_NPL_EVENT_COUNT ((MYNEWT_VAL(BLE_MULTI_ADV_INSTANCES)+1)*3)
#define ADV_LL_NPL_EVENT_COUNT ((BT_LE_MAX_EXT_ADV_INSTANCES+1)*3)
#define SCAN_LL_NPL_EVENT_COUNT (2)
#define RL_LL_NPL_EVENT_COUNT (1)
#define SYNC_LL_NPL_EVENT_COUNT (7)
@@ -84,7 +98,8 @@ static const char *TAG = "Timer";
#define LL_CFG_FEAT_LE_PING_EVT (0)
#endif
#define CONN_MODULE_NPL_EVENT_COUNT (((LL_CFG_FEAT_LE_PING_EVT+2)*MYNEWT_VAL(BLE_MAX_CONNECTIONS))+LL_CTRL_TO_HOST_FLOW_CTRL_EVT)
#define CONN_MODULE_NPL_EVENT_COUNT (((LL_CFG_FEAT_LE_PING_EVT+2)*BT_LE_MAX_CONNECTIONS)+LL_CTRL_TO_HOST_FLOW_CTRL_EVT)
#define BLE_LL_EV_COUNT (LL_NPL_BASE_EVENT_COUNT + \
LL_SCAN_EXT_AUX_EVT_CNT + \
@@ -99,7 +114,7 @@ static const char *TAG = "Timer";
#define BLE_TOTAL_EVQ_COUNT (10)
#define BLE_TOTAL_CO_COUNT (20)
#define BLE_TOTAL_CO_COUNT (40)
#define BLE_TOTAL_SEM_COUNT (10)
@@ -1013,15 +1028,22 @@ IRAM_ATTR npl_freertos_callout_set_arg(struct ble_npl_callout *co, void *arg)
uint32_t
IRAM_ATTR npl_freertos_time_get(void)
{
#if CONFIG_BT_NIMBLE_USE_ESP_TIMER
return esp_timer_get_time() / 1000;
#else
return xTaskGetTickCountFromISR();
#endif
}
ble_npl_error_t
IRAM_ATTR npl_freertos_time_ms_to_ticks(uint32_t ms, ble_npl_time_t *out_ticks)
{
uint64_t ticks;
#if CONFIG_BT_NIMBLE_USE_ESP_TIMER
ticks = (uint64_t)ms;
#else
ticks = ((uint64_t)ms * configTICK_RATE_HZ) / 1000;
#endif
if (ticks > UINT32_MAX) {
return BLE_NPL_EINVAL;
}
@@ -1035,8 +1057,11 @@ ble_npl_error_t
IRAM_ATTR npl_freertos_time_ticks_to_ms(ble_npl_time_t ticks, uint32_t *out_ms)
{
uint64_t ms;
#if CONFIG_BT_NIMBLE_USE_ESP_TIMER
ms = ((uint64_t)ticks);
#else
ms = ((uint64_t)ticks * 1000) / configTICK_RATE_HZ;
#endif
if (ms > UINT32_MAX) {
return BLE_NPL_EINVAL;
}
@@ -1049,19 +1074,31 @@ IRAM_ATTR npl_freertos_time_ticks_to_ms(ble_npl_time_t ticks, uint32_t *out_ms)
ble_npl_time_t
IRAM_ATTR npl_freertos_time_ms_to_ticks32(uint32_t ms)
{
#if CONFIG_BT_NIMBLE_USE_ESP_TIMER
return ms;
#else
return ms * configTICK_RATE_HZ / 1000;
#endif
}
uint32_t
IRAM_ATTR npl_freertos_time_ticks_to_ms32(ble_npl_time_t ticks)
{
#if CONFIG_BT_NIMBLE_USE_ESP_TIMER
return ticks;
#else
return ticks * 1000 / configTICK_RATE_HZ;
#endif
}
void
IRAM_ATTR npl_freertos_time_delay(ble_npl_time_t ticks)
{
#if CONFIG_BT_NIMBLE_USE_ESP_TIMER
vTaskDelay(ticks / portTICK_PERIOD_MS);
#else
vTaskDelay(ticks);
#endif
}
#ifdef ESP_PLATFORM
@@ -1734,6 +1771,10 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
void
npl_freertos_callout_deinit(struct ble_npl_callout *co)
{
if (!co->handle) {
return;
}
#if CONFIG_BT_NIMBLE_USE_ESP_TIMER
if(esp_timer_stop(co->handle))
ESP_LOGW(TAG, "Timer not stopped");
@@ -1741,9 +1782,8 @@ npl_freertos_callout_deinit(struct ble_npl_callout *co)
if(esp_timer_delete(co->handle))
ESP_LOGW(TAG, "Timer not deleted");
#else
if (co->handle) {
xTimerDelete(co->handle, portMAX_DELAY);
}
xTimerDelete(co->handle, portMAX_DELAY);
ble_npl_event_deinit(&co->ev);
#endif
memset(co, 0, sizeof(struct ble_npl_callout));
}
@@ -1787,6 +1827,9 @@ npl_freertos_callout_reset(struct ble_npl_callout *co, ble_npl_time_t ticks)
void
npl_freertos_callout_stop(struct ble_npl_callout *co)
{
if (!co->handle) {
return;
}
#if CONFIG_BT_NIMBLE_USE_ESP_TIMER
esp_timer_stop(co->handle);
#else