P4 fixes
This commit is contained in:
iranl
@@ -0,0 +1,25 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** prevent recursive inclusion **/
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#ifndef __ESP_HOSTED_API_TYPES_H__
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#define __ESP_HOSTED_API_TYPES_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint32_t major1;
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uint32_t minor1;
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uint32_t patch1;
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} esp_hosted_coprocessor_fwver_t;
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -0,0 +1,54 @@
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/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ESP_HOSTED_BT_CONFIG_H__
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#define __ESP_HOSTED_BT_CONFIG_H__
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// check: if co-processor SOC is ESP32, only BT BLE 4.2 is supported
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#if CONFIG_SLAVE_IDF_TARGET_ESP32
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#if CONFIG_BT_BLE_50_FEATURES_SUPPORTED || CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT
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#error "ESP32 co-processor only supports BLE 4.2"
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#endif
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#endif
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// Hosted BT defines for NimBLE
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#if CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE
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#define H_BT_HOST_ESP_NIMBLE 1
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#else
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#define H_BT_HOST_ESP_NIMBLE 0
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#endif
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#if CONFIG_ESP_HOSTED_NIMBLE_HCI_VHCI
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#define H_BT_USE_VHCI 1
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#else
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#define H_BT_USE_VHCI 0
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#endif
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// Hosted BT defines for BlueDroid
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#if CONFIG_ESP_HOSTED_ENABLE_BT_BLUEDROID
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#define H_BT_HOST_ESP_BLUEDROID 1
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#else
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#define H_BT_HOST_ESP_BLUEDROID 0
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#endif
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#if CONFIG_ESP_HOSTED_BLUEDROID_HCI_VHCI
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#define H_BT_BLUEDROID_USE_VHCI 1
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#else
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#define H_BT_BLUEDROID_USE_VHCI 1
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#endif
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#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 0)
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// ll_init required
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#define H_BT_ENABLE_LL_INIT 1
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#else
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#define H_BT_ENABLE_LL_INIT 0
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#endif
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// check: only one BT host stack can be enabled at a time
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#if H_BT_HOST_ESP_NIMBLE && H_BT_HOST_ESP_BLUEDROID
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#error "Enable only NimBLE or BlueDroid, not both"
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#endif
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#endif
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@@ -0,0 +1,396 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ESP_HOSTED_CONFIG_H__
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#define __ESP_HOSTED_CONFIG_H__
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#include "sdkconfig.h"
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#include "esp_task.h"
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#define H_TRANSPORT_NONE 0
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#define H_TRANSPORT_SDIO 1
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#define H_TRANSPORT_SPI_HD 2
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#define H_TRANSPORT_SPI 3
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#define H_TRANSPORT_UART 4
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#ifdef CONFIG_ESP_HOSTED_UART_HOST_INTERFACE
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#include "hal/uart_types.h"
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#endif
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/* This file is to tune the main ESP-Hosted configurations.
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* In case you are not sure of some value, Let it be default.
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**/
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#define H_GPIO_LOW 0
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#define H_GPIO_HIGH 1
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enum {
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H_GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */
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H_GPIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */
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H_GPIO_INTR_NEGEDGE = 2, /*!< GPIO interrupt type : falling edge */
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H_GPIO_INTR_ANYEDGE = 3, /*!< GPIO interrupt type : both rising and falling edge */
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H_GPIO_INTR_LOW_LEVEL = 4, /*!< GPIO interrupt type : input low level trigger */
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H_GPIO_INTR_HIGH_LEVEL = 5, /*!< GPIO interrupt type : input high level trigger */
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H_GPIO_INTR_MAX,
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};
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#if CONFIG_SLAVE_IDF_TARGET_ESP32
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#define H_SLAVE_TARGET_ESP32 1
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#elif CONFIG_SLAVE_IDF_TARGET_ESP32S2
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#define H_SLAVE_TARGET_ESP32S2 1
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#elif CONFIG_SLAVE_IDF_TARGET_ESP32C3
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#define H_SLAVE_TARGET_ESP32C3 1
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#elif CONFIG_SLAVE_IDF_TARGET_ESP32S3
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#define H_SLAVE_TARGET_ESP32S3 1
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#elif CONFIG_SLAVE_IDF_TARGET_ESP32C2
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#define H_SLAVE_TARGET_ESP32C2 1
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#elif CONFIG_SLAVE_IDF_TARGET_ESP32C6
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#define H_SLAVE_TARGET_ESP32C6 1
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#elif CONFIG_SLAVE_IDF_TARGET_ESP32C5
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#define H_SLAVE_TARGET_ESP32C5 1
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#else
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#error "Unknown Slave Target"
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#endif
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#if CONFIG_ESP_HOSTED_USE_MEMPOOL
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#define H_USE_MEMPOOL 1
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#endif
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#define H_MAX_SYNC_RPC_REQUESTS CONFIG_ESP_HOSTED_MAX_SIMULTANEOUS_SYNC_RPC_REQUESTS
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#define H_MAX_ASYNC_RPC_REQUESTS CONFIG_ESP_HOSTED_MAX_SIMULTANEOUS_ASYNC_RPC_REQUESTS
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#undef H_TRANSPORT_IN_USE
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#ifdef CONFIG_ESP_HOSTED_SPI_HOST_INTERFACE
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#define H_TRANSPORT_IN_USE H_TRANSPORT_SPI
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/* -------------------------- SPI Master Config start ---------------------- */
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/*
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Pins in use. The SPI Master can use the GPIO mux,
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so feel free to change these if needed.
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*/
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/* SPI config */
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#ifdef CONFIG_ESP_HOSTED_HS_ACTIVE_LOW
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#define H_HANDSHAKE_ACTIVE_HIGH 0
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#else
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/* Default HS: Active High */
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#define H_HANDSHAKE_ACTIVE_HIGH 1
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#endif
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#ifdef CONFIG_ESP_HOSTED_DR_ACTIVE_LOW
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#define H_DATAREADY_ACTIVE_HIGH 0
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#else
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/* Default DR: Active High */
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#define H_DATAREADY_ACTIVE_HIGH 1
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#endif
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#if H_HANDSHAKE_ACTIVE_HIGH
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#define H_HS_VAL_ACTIVE H_GPIO_HIGH
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#define H_HS_VAL_INACTIVE H_GPIO_LOW
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#define H_HS_INTR_EDGE H_GPIO_INTR_POSEDGE
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#else
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#define H_HS_VAL_ACTIVE H_GPIO_LOW
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#define H_HS_VAL_INACTIVE H_GPIO_HIGH
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#define H_HS_INTR_EDGE H_GPIO_INTR_NEGEDGE
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#endif
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#if H_DATAREADY_ACTIVE_HIGH
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#define H_DR_VAL_ACTIVE H_GPIO_HIGH
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#define H_DR_VAL_INACTIVE H_GPIO_LOW
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#define H_DR_INTR_EDGE H_GPIO_INTR_POSEDGE
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#else
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#define H_DR_VAL_ACTIVE H_GPIO_LOW
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#define H_DR_VAL_INACTIVE H_GPIO_HIGH
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#define H_DR_INTR_EDGE H_GPIO_INTR_NEGEDGE
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#endif
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#define H_GPIO_HANDSHAKE_Port NULL
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#define H_GPIO_HANDSHAKE_Pin CONFIG_ESP_HOSTED_SPI_GPIO_HANDSHAKE
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#define H_GPIO_DATA_READY_Port NULL
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#define H_GPIO_DATA_READY_Pin CONFIG_ESP_HOSTED_SPI_GPIO_DATA_READY
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#define H_GPIO_MOSI_Port NULL
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#define H_GPIO_MOSI_Pin CONFIG_ESP_HOSTED_SPI_GPIO_MOSI
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#define H_GPIO_MISO_Port NULL
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#define H_GPIO_MISO_Pin CONFIG_ESP_HOSTED_SPI_GPIO_MISO
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#define H_GPIO_SCLK_Port NULL
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#define H_GPIO_SCLK_Pin CONFIG_ESP_HOSTED_SPI_GPIO_CLK
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#define H_GPIO_CS_Port NULL
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#define H_GPIO_CS_Pin CONFIG_ESP_HOSTED_SPI_GPIO_CS
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#define H_SPI_TX_Q CONFIG_ESP_HOSTED_SPI_TX_Q_SIZE
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#define H_SPI_RX_Q CONFIG_ESP_HOSTED_SPI_RX_Q_SIZE
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#define H_SPI_MODE CONFIG_ESP_HOSTED_SPI_MODE
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#define H_SPI_INIT_CLK_MHZ CONFIG_ESP_HOSTED_SPI_CLK_FREQ
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/* -------------------------- SPI Master Config end ------------------------ */
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#endif
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#ifdef CONFIG_ESP_HOSTED_SDIO_HOST_INTERFACE
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#define H_TRANSPORT_IN_USE H_TRANSPORT_SDIO
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/* -------------------------- SDIO Host Config start ----------------------- */
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#ifdef CONFIG_SOC_SDMMC_USE_GPIO_MATRIX
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#define H_SDIO_SOC_USE_GPIO_MATRIX
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#endif
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#define H_SDIO_CLOCK_FREQ_KHZ CONFIG_ESP_HOSTED_SDIO_CLOCK_FREQ_KHZ
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#define H_SDIO_BUS_WIDTH CONFIG_ESP_HOSTED_SDIO_BUS_WIDTH
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#define H_SDMMC_HOST_SLOT CONFIG_ESP_HOSTED_SDIO_SLOT
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#ifdef H_SDIO_SOC_USE_GPIO_MATRIX
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#define H_SDIO_PIN_CLK CONFIG_ESP_HOSTED_SDIO_PIN_CLK
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#define H_SDIO_PIN_CMD CONFIG_ESP_HOSTED_SDIO_PIN_CMD
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#define H_SDIO_PIN_D0 CONFIG_ESP_HOSTED_SDIO_PIN_D0
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#define H_SDIO_PIN_D1 CONFIG_ESP_HOSTED_SDIO_PIN_D1
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#if (H_SDIO_BUS_WIDTH == 4)
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#define H_SDIO_PIN_D2 CONFIG_ESP_HOSTED_SDIO_PIN_D2
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#define H_SDIO_PIN_D3 CONFIG_ESP_HOSTED_SDIO_PIN_D3
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#else
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#define H_SDIO_PIN_D2 -1
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#define H_SDIO_PIN_D3 -1
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#endif
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#else
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#define H_SDIO_PIN_CLK -1
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#define H_SDIO_PIN_CMD -1
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#define H_SDIO_PIN_D0 -1
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#define H_SDIO_PIN_D1 -1
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#if (H_SDIO_BUS_WIDTH == 4)
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#define H_SDIO_PIN_D2 -1
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#define H_SDIO_PIN_D3 -1
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#else
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#define H_SDIO_PIN_D2 -1
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#define H_SDIO_PIN_D3 -1
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#endif
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#endif
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#define H_SDIO_TX_Q CONFIG_ESP_HOSTED_SDIO_TX_Q_SIZE
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#define H_SDIO_RX_Q CONFIG_ESP_HOSTED_SDIO_RX_Q_SIZE
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#define H_SDIO_CHECKSUM CONFIG_ESP_HOSTED_SDIO_CHECKSUM
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#define H_SDIO_HOST_STREAMING_MODE 1
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#define H_SDIO_ALWAYS_HOST_RX_MAX_TRANSPORT_SIZE 2
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#define H_SDIO_OPTIMIZATION_RX_NONE 3
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#ifdef CONFIG_ESP_HOSTED_SDIO_OPTIMIZATION_RX_STREAMING_MODE
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#define H_SDIO_HOST_RX_MODE H_SDIO_HOST_STREAMING_MODE
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#elif defined(CONFIG_ESP_HOSTED_SDIO_OPTIMIZATION_RX_MAX_SIZE)
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#define H_SDIO_HOST_RX_MODE H_SDIO_ALWAYS_HOST_RX_MAX_TRANSPORT_SIZE
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#else
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/* Use this if unsure */
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#define H_SDIO_HOST_RX_MODE H_SDIO_OPTIMIZATION_RX_NONE
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#endif
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// Pad transfer len for host operation
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#define H_SDIO_TX_LEN_TO_TRANSFER(x) ((x + 3) & (~3))
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#define H_SDIO_RX_LEN_TO_TRANSFER(x) ((x + 3) & (~3))
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/* Do Block Mode only transfers
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*
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* When enabled, SDIO only uses block mode transfers for higher
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* throughput. Data lengths are padded to multiples of ESP_BLOCK_SIZE.
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*
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* This is safe for the SDIO slave:
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* - for Host Tx: slave will ignore extra data sent by Host
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* - for Host Rx: slave will send extra 0 data, ignored by Host
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*/
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#define H_SDIO_TX_BLOCK_ONLY_XFER (1)
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#define H_SDIO_RX_BLOCK_ONLY_XFER (1)
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// workarounds for some SDIO transfer errors that may occur
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#if 0
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/* Below workarounds could be enabled for non-ESP MCUs to test first
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* Once everything is stable, can disable workarounds and test again
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* */
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#define H_SDIO_TX_LIMIT_XFER_SIZE_WORKAROUND // limit transfer to one ESP_BLOCK_SIZE at a time
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#define H_SDIO_RX_LIMIT_XFER_SIZE_WORKDAROUND // limit transfer to one ESP_BLOCK_SIZE at a time
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#endif
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#if defined(H_SDIO_TX_LIMIT_XFER_SIZE_WORKAROUND)
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#define H_SDIO_TX_BLOCKS_TO_TRANSFER(x) (1)
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#else
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#define H_SDIO_TX_BLOCKS_TO_TRANSFER(x) (x / ESP_BLOCK_SIZE)
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#endif
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#if defined(H_SDIO_RX_LIMIT_XFER_SIZE_WORKDAROUND)
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#define H_SDIO_RX_BLOCKS_TO_TRANSFER(x) (1)
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#else
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#define H_SDIO_RX_BLOCKS_TO_TRANSFER(x) (x / ESP_BLOCK_SIZE)
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#endif
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/* -------------------------- SDIO Host Config end ------------------------- */
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#endif
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#ifdef CONFIG_ESP_HOSTED_SPI_HD_HOST_INTERFACE
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#define H_TRANSPORT_IN_USE H_TRANSPORT_SPI_HD
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/* -------------------------- SPI_HD Host Config start ----------------------- */
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#define H_SPI_HD_HOST_INTERFACE 1
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enum {
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H_SPI_HD_CONFIG_2_DATA_LINES,
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H_SPI_HD_CONFIG_4_DATA_LINES,
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};
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#if CONFIG_ESP_HOSTED_SPI_HD_DR_ACTIVE_HIGH
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#define H_SPI_HD_DATAREADY_ACTIVE_HIGH 1
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#else
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#define H_SPI_HD_DATAREADY_ACTIVE_HIGH 0
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#endif
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#if H_SPI_HD_DATAREADY_ACTIVE_HIGH
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#define H_SPI_HD_DR_VAL_ACTIVE H_GPIO_HIGH
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#define H_SPI_HD_DR_VAL_INACTIVE H_GPIO_LOW
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#define H_SPI_HD_DR_INTR_EDGE H_GPIO_INTR_POSEDGE
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#else
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#define H_SPI_HD_DR_VAL_ACTIVE H_GPIO_LOW
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#define H_SPI_HD_DR_VAL_INACTIVE H_GPIO_HIGH
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#define H_SPI_HD_DR_INTR_EDGE H_GPIO_INTR_NEGEDGE
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#endif
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#define H_SPI_HD_HOST_NUM_DATA_LINES CONFIG_ESP_HOSTED_SPI_HD_INTERFACE_NUM_DATA_LINES
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#define H_SPI_HD_PIN_D0 CONFIG_ESP_HOSTED_SPI_HD_GPIO_D0
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#define H_SPI_HD_PIN_D1 CONFIG_ESP_HOSTED_SPI_HD_GPIO_D1
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#if (CONFIG_ESP_HOSTED_SPI_HD_INTERFACE_NUM_DATA_LINES == 4)
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#define H_SPI_HD_PIN_D2 CONFIG_ESP_HOSTED_SPI_HD_GPIO_D2
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#define H_SPI_HD_PIN_D3 CONFIG_ESP_HOSTED_SPI_HD_GPIO_D3
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#else
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#define H_SPI_HD_PIN_D2 -1
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#define H_SPI_HD_PIN_D3 -1
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#endif
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#define H_SPI_HD_PIN_CS CONFIG_ESP_HOSTED_SPI_HD_GPIO_CS
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#define H_SPI_HD_PIN_CLK CONFIG_ESP_HOSTED_SPI_HD_GPIO_CLK
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#define H_SPI_HD_GPIO_DATA_READY_Port NULL
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#define H_SPI_HD_PIN_DATA_READY CONFIG_ESP_HOSTED_SPI_HD_GPIO_DATA_READY
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#define H_SPI_HD_CLK_MHZ CONFIG_ESP_HOSTED_SPI_HD_CLK_FREQ
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#define H_SPI_HD_MODE CONFIG_ESP_HOSTED_SPI_HD_MODE
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#define H_SPI_HD_TX_QUEUE_SIZE CONFIG_ESP_HOSTED_SPI_HD_TX_Q_SIZE
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#define H_SPI_HD_RX_QUEUE_SIZE CONFIG_ESP_HOSTED_SPI_HD_RX_Q_SIZE
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#define H_SPI_HD_CHECKSUM CONFIG_ESP_HOSTED_SPI_HD_CHECKSUM
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#define H_SPI_HD_NUM_COMMAND_BITS 8
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#define H_SPI_HD_NUM_ADDRESS_BITS 8
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#define H_SPI_HD_NUM_DUMMY_BITS 8
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/* -------------------------- SPI_HD Host Config end ------------------------- */
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#else
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#define H_SPI_HD_HOST_INTERFACE 0
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#endif
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#ifdef CONFIG_ESP_HOSTED_UART_HOST_INTERFACE
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#define H_TRANSPORT_IN_USE H_TRANSPORT_UART
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/* -------------------------- UART Host Config start ------------------------- */
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#define H_UART_HOST_TRANSPORT 1
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#define H_UART_PORT CONFIG_ESP_HOSTED_UART_PORT
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#define H_UART_NUM_DATA_BITS CONFIG_ESP_HOSTED_UART_NUM_DATA_BITS
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#define H_UART_PARITY CONFIG_ESP_HOSTED_UART_PARITY
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#define H_UART_START_BITS 1
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#define H_UART_STOP_BITS CONFIG_ESP_HOSTED_UART_STOP_BITS
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#define H_UART_FLOWCTRL UART_HW_FLOWCTRL_DISABLE
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#define H_UART_CLK_SRC UART_SCLK_DEFAULT
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#define H_UART_CHECKSUM CONFIG_ESP_HOSTED_UART_CHECKSUM
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#define H_UART_BAUD_RATE CONFIG_ESP_HOSTED_UART_BAUDRATE
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#define H_UART_TX_PIN CONFIG_ESP_HOSTED_UART_PIN_TX
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#define H_UART_RX_PIN CONFIG_ESP_HOSTED_UART_PIN_RX
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#define H_UART_TX_QUEUE_SIZE CONFIG_ESP_HOSTED_UART_TX_Q_SIZE
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#define H_UART_RX_QUEUE_SIZE CONFIG_ESP_HOSTED_UART_RX_Q_SIZE
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/* -------------------------- UART Host Config end ------------------------- */
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#else
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#define H_UART_HOST_TRANSPORT 0
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#endif
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/* Generic reset pin config */
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#define H_GPIO_PIN_RESET_Port NULL
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#define H_GPIO_PIN_RESET_Pin CONFIG_ESP_HOSTED_GPIO_SLAVE_RESET_SLAVE
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/* If Reset pin is Enable, it is Active High.
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* If it is RST, active low */
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#ifdef CONFIG_ESP_HOSTED_RESET_GPIO_ACTIVE_LOW
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#define H_RESET_ACTIVE_HIGH 0
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#else
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#define H_RESET_ACTIVE_HIGH 1
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#endif
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#if H_RESET_ACTIVE_HIGH
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#define H_RESET_VAL_ACTIVE H_GPIO_HIGH
|
||||
#define H_RESET_VAL_INACTIVE H_GPIO_LOW
|
||||
#else
|
||||
#define H_RESET_VAL_ACTIVE H_GPIO_LOW
|
||||
#define H_RESET_VAL_INACTIVE H_GPIO_HIGH
|
||||
#endif
|
||||
|
||||
|
||||
#define TIMEOUT_PSERIAL_RESP 30
|
||||
|
||||
|
||||
#define PRE_FORMAT_NEWLINE_CHAR ""
|
||||
#define POST_FORMAT_NEWLINE_CHAR "\n"
|
||||
|
||||
#define USE_STD_C_LIB_MALLOC 0
|
||||
|
||||
#ifdef CONFIG_HOST_TO_ESP_WIFI_DATA_THROTTLE
|
||||
#define H_WIFI_TX_DATA_THROTTLE_LOW_THRESHOLD CONFIG_ESP_HOSTED_TO_WIFI_DATA_THROTTLE_LOW_THRESHOLD
|
||||
#define H_WIFI_TX_DATA_THROTTLE_HIGH_THRESHOLD CONFIG_ESP_HOSTED_TO_WIFI_DATA_THROTTLE_HIGH_THRESHOLD
|
||||
#else
|
||||
#define H_WIFI_TX_DATA_THROTTLE_LOW_THRESHOLD 0
|
||||
#define H_WIFI_TX_DATA_THROTTLE_HIGH_THRESHOLD 0
|
||||
#endif
|
||||
|
||||
#define H_PKT_STATS CONFIG_ESP_HOSTED_PKT_STATS
|
||||
|
||||
/* Raw Throughput Testing */
|
||||
#define H_TEST_RAW_TP CONFIG_ESP_HOSTED_RAW_THROUGHPUT_TRANSPORT
|
||||
|
||||
#if H_TEST_RAW_TP
|
||||
#define H_RAW_TP_REPORT_INTERVAL CONFIG_ESP_HOSTED_RAW_TP_REPORT_INTERVAL
|
||||
#define H_RAW_TP_PKT_LEN CONFIG_ESP_HOSTED_RAW_TP_HOST_TO_ESP_PKT_LEN
|
||||
|
||||
#if CONFIG_ESP_HOSTED_RAW_THROUGHPUT_TX_TO_SLAVE
|
||||
#define H_TEST_RAW_TP_DIR (ESP_TEST_RAW_TP__HOST_TO_ESP)
|
||||
#elif CONFIG_ESP_HOSTED_RAW_THROUGHPUT_RX_FROM_SLAVE
|
||||
#define H_TEST_RAW_TP_DIR (ESP_TEST_RAW_TP__ESP_TO_HOST)
|
||||
#elif CONFIG_ESP_HOSTED_RAW_THROUGHPUT_BIDIRECTIONAL
|
||||
#define H_TEST_RAW_TP_DIR (ESP_TEST_RAW_TP__BIDIRECTIONAL)
|
||||
#else
|
||||
#error Test Raw TP direction not defined
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define H_TEST_RAW_TP_DIR (ESP_TEST_RAW_TP_NONE)
|
||||
#endif
|
||||
|
||||
/* ---------------------- ESP-IDF Specific Config start -------------------- */
|
||||
/* This section is for ESP-IDF specific support.
|
||||
* Can be ignored on other hosts MCUs.
|
||||
*/
|
||||
|
||||
/* Controls whether an Internal LDO powers the SDIO connection */
|
||||
#if CONFIG_ESP_HOSTED_SD_PWR_CTRL_LDO_INTERNAL_IO
|
||||
#define H_SDIO_PWR_CTRL_LDO 1
|
||||
#define H_SDIO_PWR_CTRL_LDO_ID CONFIG_ESP_HOSTED_SD_PWR_CTRL_LDO_IO_ID
|
||||
#else
|
||||
#define H_SDIO_PWR_CTRL_LDO 0
|
||||
#endif
|
||||
|
||||
/* ---------------------- ESP-IDF Specific Config end ---------------------- */
|
||||
|
||||
esp_err_t esp_hosted_set_default_config(void);
|
||||
bool esp_hosted_is_config_valid(void);
|
||||
|
||||
#endif /*__ESP_HOSTED_CONFIG_H__*/
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* APIs to do OTA updates of the co-processor
|
||||
*
|
||||
* Note: This API is platform dependent
|
||||
*
|
||||
* Add additional APIs as required based on how the OTA binary is to
|
||||
* be fetched.
|
||||
*
|
||||
* Source for the API should be in host/port/<platform>/...
|
||||
*
|
||||
* Procedure used by APIs to do OTA update:
|
||||
* 1. Fetch and prepare OTA binary
|
||||
* 2. Call rpc_ota_begin() to start OTA
|
||||
* 3. Repeatedly call rpc_ota_write() with a continuous chunk of OTA data
|
||||
* 4. Call rpc_ota_end()
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ESP_HOSTED_OTA_H__
|
||||
#define __ESP_HOSTED_OTA_H__
|
||||
|
||||
#ifdef ESP_PLATFORM
|
||||
// OTA API for ESP-IDF
|
||||
#include "esp_err.h"
|
||||
|
||||
/* Fetch OTA image from a web server (image_url) */
|
||||
esp_err_t esp_hosted_slave_ota(const char* image_url);
|
||||
#endif
|
||||
|
||||
#endif /*__ESP_HOSTED_OTA_H__*/
|
||||
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __ESP_HOSTED_TRANSPORT_CONFIG_H__
|
||||
#define __ESP_HOSTED_TRANSPORT_CONFIG_H__
|
||||
|
||||
#include "esp_hosted_config.h"
|
||||
#include "esp_err.h"
|
||||
|
||||
typedef enum {
|
||||
ESP_TRANSPORT_OK = ESP_OK,
|
||||
ESP_TRANSPORT_ERR_INVALID_ARG = ESP_ERR_INVALID_ARG,
|
||||
ESP_TRANSPORT_ERR_ALREADY_SET = ESP_ERR_NOT_ALLOWED,
|
||||
ESP_TRANSPORT_ERR_INVALID_STATE = ESP_ERR_INVALID_STATE,
|
||||
} esp_hosted_transport_err_t;
|
||||
|
||||
/* GPIO pin configuration structure */
|
||||
typedef struct {
|
||||
void *port;
|
||||
uint8_t pin;
|
||||
} gpio_pin_t;
|
||||
|
||||
/* New Configuration Structures */
|
||||
struct esp_hosted_sdio_config {
|
||||
uint32_t clock_freq_khz;
|
||||
uint8_t bus_width;
|
||||
uint8_t slot;
|
||||
gpio_pin_t pin_clk;
|
||||
gpio_pin_t pin_cmd;
|
||||
gpio_pin_t pin_d0;
|
||||
gpio_pin_t pin_d1;
|
||||
gpio_pin_t pin_d2;
|
||||
gpio_pin_t pin_d3;
|
||||
gpio_pin_t pin_reset;
|
||||
uint8_t rx_mode;
|
||||
bool block_mode;
|
||||
bool iomux_enable;
|
||||
};
|
||||
|
||||
struct esp_hosted_spi_hd_config {
|
||||
/* Number of lines used */
|
||||
uint8_t num_data_lines;
|
||||
|
||||
/* SPI HD pins */
|
||||
gpio_pin_t pin_cs;
|
||||
gpio_pin_t pin_clk;
|
||||
gpio_pin_t pin_data_ready;
|
||||
gpio_pin_t pin_d0;
|
||||
gpio_pin_t pin_d1;
|
||||
gpio_pin_t pin_d2;
|
||||
gpio_pin_t pin_d3;
|
||||
gpio_pin_t pin_reset;
|
||||
|
||||
/* SPI HD configuration */
|
||||
uint32_t clk_mhz;
|
||||
uint8_t mode;
|
||||
uint16_t tx_queue_size;
|
||||
uint16_t rx_queue_size;
|
||||
bool checksum_enable;
|
||||
uint8_t num_command_bits;
|
||||
uint8_t num_address_bits;
|
||||
uint8_t num_dummy_bits;
|
||||
};
|
||||
|
||||
struct esp_hosted_spi_config {
|
||||
/* SPI Full Duplex pins */
|
||||
gpio_pin_t pin_mosi;
|
||||
gpio_pin_t pin_miso;
|
||||
gpio_pin_t pin_sclk;
|
||||
gpio_pin_t pin_cs;
|
||||
gpio_pin_t pin_handshake;
|
||||
gpio_pin_t pin_data_ready;
|
||||
gpio_pin_t pin_reset;
|
||||
|
||||
/* SPI Full Duplex configuration */
|
||||
uint16_t tx_queue_size;
|
||||
uint16_t rx_queue_size;
|
||||
uint8_t mode;
|
||||
uint32_t clk_mhz;
|
||||
};
|
||||
|
||||
struct esp_hosted_uart_config {
|
||||
/* UART bus number */
|
||||
uint8_t port;
|
||||
|
||||
/* UART pins */
|
||||
gpio_pin_t pin_tx;
|
||||
gpio_pin_t pin_rx;
|
||||
gpio_pin_t pin_reset;
|
||||
|
||||
/* UART configuration */
|
||||
uint8_t num_data_bits;
|
||||
uint8_t parity;
|
||||
uint8_t stop_bits;
|
||||
uint8_t flow_ctrl;
|
||||
uint8_t clk_src;
|
||||
bool checksum_enable;
|
||||
uint32_t baud_rate;
|
||||
uint16_t tx_queue_size;
|
||||
uint16_t rx_queue_size;
|
||||
};
|
||||
|
||||
struct esp_hosted_transport_config {
|
||||
uint8_t transport_in_use;
|
||||
union {
|
||||
struct esp_hosted_sdio_config sdio;
|
||||
struct esp_hosted_spi_hd_config spi_hd;
|
||||
struct esp_hosted_spi_config spi;
|
||||
struct esp_hosted_uart_config uart;
|
||||
} u;
|
||||
};
|
||||
|
||||
#if H_TRANSPORT_SDIO == H_TRANSPORT_IN_USE
|
||||
#define INIT_DEFAULT_HOST_SDIO_CONFIG() \
|
||||
(struct esp_hosted_sdio_config) { \
|
||||
.clock_freq_khz = H_SDIO_CLOCK_FREQ_KHZ, \
|
||||
.bus_width = H_SDIO_BUS_WIDTH, \
|
||||
.slot = H_SDMMC_HOST_SLOT, \
|
||||
.pin_clk = {.port = NULL, .pin = H_SDIO_PIN_CLK}, \
|
||||
.pin_cmd = {.port = NULL, .pin = H_SDIO_PIN_CMD}, \
|
||||
.pin_d0 = {.port = NULL, .pin = H_SDIO_PIN_D0}, \
|
||||
.pin_d1 = {.port = NULL, .pin = H_SDIO_PIN_D1}, \
|
||||
.pin_d2 = {.port = NULL, .pin = H_SDIO_PIN_D2}, \
|
||||
.pin_d3 = {.port = NULL, .pin = H_SDIO_PIN_D3}, \
|
||||
.pin_reset = {.port = NULL, .pin = H_GPIO_PIN_RESET_Pin }, \
|
||||
.rx_mode = H_SDIO_HOST_RX_MODE, \
|
||||
.block_mode = H_SDIO_TX_BLOCK_ONLY_XFER && H_SDIO_RX_BLOCK_ONLY_XFER, \
|
||||
.iomux_enable = false, \
|
||||
}
|
||||
|
||||
#define INIT_DEFAULT_HOST_SDIO_IOMUX_CONFIG() \
|
||||
(struct esp_hosted_sdio_config) { \
|
||||
.clock_freq_khz = H_SDIO_CLOCK_FREQ_KHZ, \
|
||||
.bus_width = H_SDIO_BUS_WIDTH, \
|
||||
.slot = H_SDMMC_HOST_SLOT, \
|
||||
.rx_mode = H_SDIO_HOST_RX_MODE, \
|
||||
.block_mode = H_SDIO_TX_BLOCK_ONLY_XFER && H_SDIO_RX_BLOCK_ONLY_XFER, \
|
||||
.iomux_enable = true, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if H_TRANSPORT_SPI_HD == H_TRANSPORT_IN_USE
|
||||
#define INIT_DEFAULT_HOST_SPI_HD_CONFIG() \
|
||||
(struct esp_hosted_spi_hd_config) { \
|
||||
.num_data_lines = H_SPI_HD_HOST_NUM_DATA_LINES, \
|
||||
.pin_cs = {.port = NULL, .pin = H_SPI_HD_PIN_CS}, \
|
||||
.pin_clk = {.port = NULL, .pin = H_SPI_HD_PIN_CLK}, \
|
||||
.pin_data_ready = {.port = NULL, .pin = H_SPI_HD_PIN_DATA_READY}, \
|
||||
.pin_d0 = {.port = NULL, .pin = H_SPI_HD_PIN_D0}, \
|
||||
.pin_d1 = {.port = NULL, .pin = H_SPI_HD_PIN_D1}, \
|
||||
.pin_d2 = {.port = NULL, .pin = H_SPI_HD_PIN_D2}, \
|
||||
.pin_d3 = {.port = NULL, .pin = H_SPI_HD_PIN_D3}, \
|
||||
.pin_reset = {.port = NULL, .pin = H_GPIO_PIN_RESET_Pin }, \
|
||||
.clk_mhz = H_SPI_HD_CLK_MHZ, \
|
||||
.mode = H_SPI_HD_MODE, \
|
||||
.tx_queue_size = H_SPI_HD_TX_QUEUE_SIZE, \
|
||||
.rx_queue_size = H_SPI_HD_RX_QUEUE_SIZE, \
|
||||
.checksum_enable = H_SPI_HD_CHECKSUM, \
|
||||
.num_command_bits = H_SPI_HD_NUM_COMMAND_BITS, \
|
||||
.num_address_bits = H_SPI_HD_NUM_ADDRESS_BITS, \
|
||||
.num_dummy_bits = H_SPI_HD_NUM_DUMMY_BITS, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if H_TRANSPORT_SPI == H_TRANSPORT_IN_USE
|
||||
#define INIT_DEFAULT_HOST_SPI_CONFIG() \
|
||||
(struct esp_hosted_spi_config) { \
|
||||
.pin_mosi = {.port = NULL, .pin = H_GPIO_MOSI_Pin}, \
|
||||
.pin_miso = {.port = NULL, .pin = H_GPIO_MISO_Pin}, \
|
||||
.pin_sclk = {.port = NULL, .pin = H_GPIO_SCLK_Pin}, \
|
||||
.pin_cs = {.port = NULL, .pin = H_GPIO_CS_Pin}, \
|
||||
.pin_handshake = {.port = NULL, .pin = H_GPIO_HANDSHAKE_Pin}, \
|
||||
.pin_data_ready = {.port = NULL, .pin = H_GPIO_DATA_READY_Pin}, \
|
||||
.pin_reset = {.port = NULL, .pin = H_GPIO_PIN_RESET_Pin }, \
|
||||
.tx_queue_size = H_SPI_TX_Q, \
|
||||
.rx_queue_size = H_SPI_RX_Q, \
|
||||
.mode = H_SPI_MODE, \
|
||||
.clk_mhz = H_SPI_INIT_CLK_MHZ, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if H_TRANSPORT_UART == H_TRANSPORT_IN_USE
|
||||
#define INIT_DEFAULT_HOST_UART_CONFIG() \
|
||||
(struct esp_hosted_uart_config) { \
|
||||
.port = H_UART_PORT, \
|
||||
.pin_tx = {.port = NULL, .pin = H_UART_TX_PIN}, \
|
||||
.pin_rx = {.port = NULL, .pin = H_UART_RX_PIN}, \
|
||||
.pin_reset = {.port = NULL, .pin = H_GPIO_PIN_RESET_Pin }, \
|
||||
.num_data_bits = H_UART_NUM_DATA_BITS, \
|
||||
.parity = H_UART_PARITY, \
|
||||
.stop_bits = H_UART_STOP_BITS, \
|
||||
.flow_ctrl = H_UART_FLOWCTRL, \
|
||||
.clk_src = H_UART_CLK_SRC, \
|
||||
.checksum_enable = H_UART_CHECKSUM, \
|
||||
.baud_rate = H_UART_BAUD_RATE, \
|
||||
.tx_queue_size = H_UART_TX_QUEUE_SIZE, \
|
||||
.rx_queue_size = H_UART_RX_QUEUE_SIZE \
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configuration get/set functions */
|
||||
esp_hosted_transport_err_t esp_hosted_transport_set_default_config(void);
|
||||
esp_hosted_transport_err_t esp_hosted_transport_get_config(struct esp_hosted_transport_config **config);
|
||||
esp_hosted_transport_err_t esp_hosted_transport_get_reset_config(gpio_pin_t *pin_config);
|
||||
|
||||
bool esp_hosted_transport_is_config_valid(void);
|
||||
|
||||
#if H_TRANSPORT_SDIO == H_TRANSPORT_IN_USE
|
||||
/* SDIO functions */
|
||||
esp_hosted_transport_err_t esp_hosted_sdio_get_config(struct esp_hosted_sdio_config **config);
|
||||
esp_hosted_transport_err_t esp_hosted_sdio_set_config(struct esp_hosted_sdio_config *config) __attribute__((warn_unused_result));
|
||||
|
||||
esp_hosted_transport_err_t esp_hosted_sdio_iomux_set_config(struct esp_hosted_sdio_config *config) __attribute__((warn_unused_result));
|
||||
#endif
|
||||
|
||||
#if H_TRANSPORT_SPI_HD == H_TRANSPORT_IN_USE
|
||||
/* SPI Half Duplex functions */
|
||||
esp_hosted_transport_err_t esp_hosted_spi_hd_get_config(struct esp_hosted_spi_hd_config **config);
|
||||
esp_hosted_transport_err_t esp_hosted_spi_hd_set_config(struct esp_hosted_spi_hd_config *config) __attribute__((warn_unused_result));
|
||||
|
||||
esp_hosted_transport_err_t esp_hosted_spi_hd_2lines_get_config(struct esp_hosted_spi_hd_config **config);
|
||||
esp_hosted_transport_err_t esp_hosted_spi_hd_2lines_set_config(struct esp_hosted_spi_hd_config *config) __attribute__((warn_unused_result));
|
||||
#endif
|
||||
|
||||
#if H_TRANSPORT_SPI == H_TRANSPORT_IN_USE
|
||||
/* SPI Full Duplex functions */
|
||||
esp_hosted_transport_err_t esp_hosted_spi_get_config(struct esp_hosted_spi_config **config);
|
||||
esp_hosted_transport_err_t esp_hosted_spi_set_config(struct esp_hosted_spi_config *config) __attribute__((warn_unused_result));
|
||||
#endif
|
||||
|
||||
#if H_TRANSPORT_UART == H_TRANSPORT_IN_USE
|
||||
/* UART functions */
|
||||
esp_hosted_transport_err_t esp_hosted_uart_get_config(struct esp_hosted_uart_config **config);
|
||||
esp_hosted_transport_err_t esp_hosted_uart_set_config(struct esp_hosted_uart_config *config) __attribute__((warn_unused_result));
|
||||
#endif
|
||||
|
||||
#endif /* __ESP_HOSTED_TRANSPORT_CONFIG_H__ */
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __ESP_HOSTED_WIFI_REMOTE_GLUE_H__
|
||||
#define __ESP_HOSTED_WIFI_REMOTE_GLUE_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_hosted_interface.h"
|
||||
#include "esp_wifi_remote.h"
|
||||
#include "esp_wifi.h"
|
||||
|
||||
struct esp_remote_channel_config {
|
||||
esp_hosted_if_type_t if_type;
|
||||
bool secure;
|
||||
};
|
||||
|
||||
typedef struct esp_remote_channel_config * esp_remote_channel_config_t;
|
||||
|
||||
/* Transport/Channel related data structures and macros */
|
||||
#define ESP_HOSTED_CHANNEL_CONFIG_DEFAULT() { \
|
||||
.secure = true, \
|
||||
}
|
||||
|
||||
/* Function pointer types for channel callbacks */
|
||||
typedef esp_err_t (*esp_remote_channel_rx_fn_t)(void *h, void *buffer,
|
||||
void *buff_to_free, size_t len);
|
||||
typedef esp_err_t (*esp_remote_channel_tx_fn_t)(void *h, void *buffer, size_t len);
|
||||
|
||||
/* Transport/Channel Management API Functions - use managed component typedef */
|
||||
esp_remote_channel_t esp_hosted_add_channel(esp_remote_channel_config_t config,
|
||||
esp_remote_channel_tx_fn_t *tx, const esp_remote_channel_rx_fn_t rx);
|
||||
esp_err_t esp_hosted_remove_channel(esp_remote_channel_t channel);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ESP_HOSTED_WIFI_REMOTE_GLUE_H__ */
|
||||
Reference in New Issue
Block a user