P4 fixes

resources/espressif__esp_hosted/common/transport/esp_hosted_transport.h

@@ -0,0 +1,65 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+/* SPDX-License-Identifier: GPL-2.0-only OR Apache-2.0 */
+
+#ifndef __ESP_HOSTED_TRANSPORT__H
+#define __ESP_HOSTED_TRANSPORT__H
+
+#define PRIO_Q_SERIAL                             0
+#define PRIO_Q_BT                                 1
+#define PRIO_Q_OTHERS                             2
+#define MAX_PRIORITY_QUEUES                       3
+#define MAC_SIZE_BYTES                            6
+
+/* Serial interface */
+#define SERIAL_IF_FILE                            "/dev/esps0"
+
+/* Protobuf related info */
+/* Endpoints registered must have same string length */
+#define RPC_EP_NAME_RSP                           "RPCRsp"
+#define RPC_EP_NAME_EVT                           "RPCEvt"
+
+#define H_FLOW_CTRL_NC  0
+#define H_FLOW_CTRL_ON  1
+#define H_FLOW_CTRL_OFF 2
+
+typedef enum {
+	ESP_PACKET_TYPE_EVENT = 0x33,
+} ESP_PRIV_PACKET_TYPE;
+
+typedef enum {
+	ESP_PRIV_EVENT_INIT = 0x22,
+} ESP_PRIV_EVENT_TYPE;
+
+typedef enum {
+	HOST_CAPABILITIES=0x44,
+	RCVD_ESP_FIRMWARE_CHIP_ID,
+	SLV_CONFIG_TEST_RAW_TP,
+	SLV_CONFIG_THROTTLE_HIGH_THRESHOLD,
+	SLV_CONFIG_THROTTLE_LOW_THRESHOLD,
+} SLAVE_CONFIG_PRIV_TAG_TYPE;
+
+#define ESP_TRANSPORT_SDIO_MAX_BUF_SIZE   1536
+#define ESP_TRANSPORT_SPI_MAX_BUF_SIZE    1600
+#define ESP_TRANSPORT_SPI_HD_MAX_BUF_SIZE 1600
+#define ESP_TRANSPORT_UART_MAX_BUF_SIZE   1600
+
+struct esp_priv_event {
+	uint8_t		event_type;
+	uint8_t		event_len;
+	uint8_t		event_data[0];
+}__attribute__((packed));
+
+static inline uint16_t compute_checksum(uint8_t *buf, uint16_t len)
+{
+	uint16_t checksum = 0;
+	uint16_t i = 0;
+
+	while(i < len) {
+		checksum += buf[i];
+		i++;
+	}
+
+	return checksum;
+}
+
+#endif

resources/espressif__esp_hosted/common/transport/esp_hosted_transport_init.h

@@ -0,0 +1,60 @@
+// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
+/* SPDX-License-Identifier: GPL-2.0-only OR Apache-2.0 */
+
+/* Definitions used in ESP-Hosted Transport Initialization */
+
+#ifndef __ESP_HOSTED_TRANSPORT_INIT__H
+#define __ESP_HOSTED_TRANSPORT_INIT__H
+
+typedef enum {
+	ESP_OPEN_DATA_PATH,
+	ESP_CLOSE_DATA_PATH,
+	ESP_RESET,
+	ESP_MAX_HOST_INTERRUPT,
+} ESP_HOST_INTERRUPT;
+
+typedef enum {
+	ESP_WLAN_SDIO_SUPPORT = (1 << 0),
+	ESP_BT_UART_SUPPORT = (1 << 1), // HCI over UART
+	ESP_BT_SDIO_SUPPORT = (1 << 2),
+	ESP_BLE_ONLY_SUPPORT = (1 << 3),
+	ESP_BR_EDR_ONLY_SUPPORT = (1 << 4),
+	ESP_WLAN_SPI_SUPPORT = (1 << 5),
+	ESP_BT_SPI_SUPPORT = (1 << 6),
+	ESP_CHECKSUM_ENABLED = (1 << 7),
+} ESP_CAPABILITIES;
+
+typedef enum {
+	// spi hd capabilities
+	ESP_SPI_HD_INTERFACE_SUPPORT_2_DATA_LINES = (1 << 0),
+	ESP_SPI_HD_INTERFACE_SUPPORT_4_DATA_LINES = (1 << 1),
+	// leave a gap for future expansion
+
+	// features supported
+	ESP_WLAN_SUPPORT         = (1 << 4),
+	ESP_BT_INTERFACE_SUPPORT = (1 << 5), // bt supported over current interface
+	// leave a gap for future expansion
+
+	// Hosted UART interface
+	ESP_WLAN_UART_SUPPORT = (1 << 8),
+	ESP_BT_VHCI_UART_SUPPORT = (1 << 9), // VHCI over UART
+} ESP_EXTENDED_CAPABILITIES;
+
+typedef enum {
+	ESP_TEST_RAW_TP_NONE = 0,
+	ESP_TEST_RAW_TP = (1 << 0),
+	ESP_TEST_RAW_TP__ESP_TO_HOST = (1 << 1),
+	ESP_TEST_RAW_TP__HOST_TO_ESP = (1 << 2),
+	ESP_TEST_RAW_TP__BIDIRECTIONAL = (1 << 3),
+} ESP_RAW_TP_MEASUREMENT;
+
+typedef enum {
+	ESP_PRIV_CAPABILITY=0x11,
+	ESP_PRIV_FIRMWARE_CHIP_ID,
+	ESP_PRIV_TEST_RAW_TP,
+	ESP_PRIV_RX_Q_SIZE,
+	ESP_PRIV_TX_Q_SIZE,
+	ESP_PRIV_CAP_EXT, // extended capability (4 bytes)
+} ESP_PRIV_TAG_TYPE;
+
+#endif

resources/espressif__esp_hosted/common/transport/esp_hosted_transport_spi_hd.h

@@ -0,0 +1,38 @@
+// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
+/* SPDX-License-Identifier: GPL-2.0-only OR Apache-2.0 */
+
+/* Definitions used in ESP-Hosted SPI-HD Transport  */
+
+#ifndef __ESP_HOSTED_TRANSPORT_SPI_HD__H
+#define __ESP_HOSTED_TRANSPORT_SPI_HD__H
+
+#define SPI_HD_HOST_24_BIT_TX_INT  1
+
+/* use upper 8 bits of tx buf len register as interrupt control bits
+ * host sends CMD9 to clear the register */
+#define SPI_HD_TX_BUF_LEN_MASK  (0x00FFFFFF)
+
+#define SPI_HD_INT_MASK           (3 << 24)
+#define SPI_HD_INT_START_THROTTLE (1 << 24)
+#define SPI_HD_INT_STOP_THROTTLE  (1 << 25)
+
+/** Slave Registers used for SPI Half-Duplex mode transfers */
+typedef enum {
+	SPI_HD_REG_SLAVE_READY     = 0x00,
+	SPI_HD_REG_MAX_TX_BUF_LEN  = 0x04,
+	SPI_HD_REG_MAX_RX_BUF_LEN  = 0x08,
+	SPI_HD_REG_TX_BUF_LEN      = 0x0C, // updated when slave wants to tx data
+	SPI_HD_REG_RX_BUF_LEN      = 0x10, // updated when slave can rx data
+	SPI_HD_REG_SLAVE_CTRL      = 0x14, // to control the slave
+} SLAVE_CONFIG_SPI_HD_REGISTERS;
+
+typedef enum {
+	SPI_HD_STATE_SLAVE_READY = 0xEE, // Slave SPI is ready
+} SLAVE_CONFIG_SPI_HD_STATE;
+
+// slave control bits
+typedef enum {
+	SPI_HD_CTRL_DATAPATH_ON  = (1 << 0),
+} SLAVE_CTRL_MASK;
+
+#endif